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TLV320AIC3104IRHBT Datasheet(PDF) 11 Page - Texas Instruments |
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TLV320AIC3104IRHBT Datasheet(HTML) 11 Page - Texas Instruments |
11 / 97 page 11 TLV320AIC3104 www.ti.com SLAS510F – FEBRUARY 2007 – REVISED DECEMBER 2016 Product Folder Links: TLV320AIC3104 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Audio Data Serial Interface Timing Requirements (1)(2) (continued) IOVDD = 1.1 V IOVDD = 3.3 V UNIT MIN MAX MIN MAX tf Fall time 30 10 ns DSP TIMING IN MASTER MODE (See Figure 2) td(WS) ADWS/WCLK delay time 50 15 ns td(DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 30 10 ns tf Fall time 30 10 ns I2S/LJF/RJF TIMING IN SLAVE MODE (See Figure 3) tH(BCLK) BCLK high period 70 35 ns tL(BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 6 ns th(WS) ADWS/WCLK hold time 10 6 ns td(DO-WS) ADWS/WCLK to DOUT delay time (for LJF Mode only) 50 35 ns td(DO-BCLK) BCLK to DOUT delay time 50 20 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 8 4 ns tf Fall time 8 4 ns DSP TIMING IN SLAVE MODE (See Figure 4) tH(BCLK) BCLK high period 70 35 ns tL(BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 8 ns th(WS) ADWS/WCLK hold time 10 8 ns td(DO-BCLK) BCLK to DOUT delay time 50 20 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 8 4 ns tf Fall time 8 4 ns |
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