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TMS320C6748EZWTD4E Datasheet(PDF) 10 Page - Texas Instruments |
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TMS320C6748EZWTD4E Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 273 page  Instruction Fetch C674x Fixed/Floating Point CPU Register File A Register File B Cache Control Memory Protect Bandwidth Mgmt L1P 256 Cache Control Memory Protect Bandwidth Mgmt L1D 64 64 8 x 32 32K Bytes L1D RAM/ Cache 32K Bytes L1P RAM/ Cache 256 Cache Control Memory Protect Bandwidth Mgmt L2 256K Bytes L2 RAM 256 BOOT ROM 256 CFG MDMA SDMA EMC Power Down Interrupt Controller IDMA 256 256 256 256 256 64 High Performance Switch Fabric 64 64 64 Configuration Peripherals Bus 32 10 TMS320C6748 SPRS590G – JUNE 2009 – REVISED JANUARY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320C6748 Device Comparison Copyright © 2009–2017, Texas Instruments Incorporated Figure 3-1. C674x Megamodule Block Diagram 3.3.1 C674x DSP CPU Description The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain 32 32- bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40- bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory. The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the C67x+ core. |
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