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TNETV2666INZWT Datasheet(PDF) 2 Page - Texas Instruments |
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TNETV2666INZWT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 249 page TMS320C6424 SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 www.ti.com • 10/100 Mb/s Ethernet MAC (EMAC) • Packages: – IEEE 802.3 Compliant – 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch – Supports Multiple Media Independent Interfaces (MII, RMII) – 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch – Management Data Input/Output (MDIO) Module • 0.09- μm/6-Level Cu Metal Process (CMOS) • VLYNQ™ Interface (FPGA Interface) • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/Q6/-Q5/-Q4) • Three Pulse Width Modulator (PWM) Outputs • 3.3-V and 1.8-V I/O, 1.05-V Internal • On-Chip ROM Bootloader (-7/-6/-5/-4/-L/-Q5) • Individual Power-Savings Modes • Applications: • Flexible PLL Clock Generators – Telecom • IEEE-1149.1 (JTAG™) – Audio Boundary-Scan-Compatible – Industrial Applications • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) • Community Resources – TI E2E Community – TI Embedded Processors Wiki 1.2 Description The TMS320C64x+™ DSPs (including the TMS320C6424 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6424 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 5600 million instructions per second (MIPS) at a clock rate of 700 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in telecom, audio, and industrial applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2800 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5600 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The C6424 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6424 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space —384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose 2 TMS320C6424 Fixed-Point Digital Signal Processor Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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