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AD9269BCPZRL7-20 Datasheet(PDF) 3 Page - Analog Devices

Part # AD9269BCPZRL7-20
Description  16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9269BCPZRL7-20 Datasheet(HTML) 3 Page - Analog Devices

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AD9269
Data Sheet
Rev. A | Page 2 of 40
TABLE OF CONTENTS
Features .............................................................................................. 1
 
Applications....................................................................................... 1
 
Functional Block Diagram .............................................................. 1
 
Product Highlights ........................................................................... 1
 
Revision History ............................................................................... 2
 
General Description ......................................................................... 3
 
Specifications..................................................................................... 4
 
DC Specifications ......................................................................... 4
 
AC Specifications.......................................................................... 6
 
Digital Specifications ................................................................... 7
 
Switching Specifications .............................................................. 8
 
Timing Specifications .................................................................. 9
 
Absolute Maximum Ratings.......................................................... 10
 
Thermal Characteristics ............................................................ 10
 
ESD Caution................................................................................ 10
 
Pin Configuration and Function Descriptions........................... 11
 
Typical Performance Characteristics ........................................... 13
 
AD9269-80 .................................................................................. 13
 
AD9269-65 .................................................................................. 15
 
AD9269-40 .................................................................................. 16
 
AD9269-20 .................................................................................. 17
 
Equivalent Circuits ......................................................................... 18
 
Theory of Operation ...................................................................... 19
 
ADC Architecture ...................................................................... 19
 
Analog Input Considerations.................................................... 19
 
Voltage Reference ....................................................................... 21
 
Clock Input Considerations...................................................... 22
 
Power Dissipation and Standby Mode .................................... 24
 
Digital Outputs ........................................................................... 25
 
Timing ......................................................................................... 25
 
Built-In Self-Test (BIST) and Output Test .................................. 26
 
Built-In Self-Test (BIST)............................................................ 26
 
Output Test Modes..................................................................... 26
 
Channel/Chip Synchronization.................................................... 27
 
DC and Quadrature Error Correction (QEC)............................ 28
 
Serial Port Interface (SPI).............................................................. 29
 
Configuration Using the SPI..................................................... 29
 
Hardware Interface..................................................................... 29
 
Configuration Without the SPI ................................................ 30
 
SPI Accessible Features.............................................................. 30
 
Memory Map .................................................................................. 31
 
Reading the Memory Map Register Table............................... 31
 
Open Locations .......................................................................... 31
 
Default Values ............................................................................. 31
 
Memory Map Register Table..................................................... 32
 
Memory Map Register Descriptions........................................ 34
 
Applications Information .............................................................. 36
 
Design Guidelines ...................................................................... 36
 
Outline Dimensions ....................................................................... 37
 
Ordering Guide .......................................................................... 37
 
REVISION HISTORY
8/2016—Rev. 0 to Rev. A
Changes to Figure 3 .................................................................................8
Updated Outline Dimensions ...............................................................37
1/2010—Revision 0: Initial Version


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