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BQ24157YFFT Datasheet(PDF) 5 Page - Texas Instruments |
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BQ24157YFFT Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 52 page  B1 C1 D1 SW PMID PGND B2 C2 D2 SW PMID PGND B3 C3 D3 SW PMID PGND B4 C4 D4 STAT SDA OTG A1 VBUS A2 VBUS A3 BOOT A4 SCL E1 CSIN E2 CD E3 VREF E4 CSOUT B1 C1 D1 SW PMID PGND B2 C2 D2 SW PMID PGND B3 C3 D3 SW PMID PGND B4 C4 D4 STAT SDA SLRST A1 VBUS A2 VBUS A3 BOOT A4 SCL E1 CSIN E2 CD E3 VREF E4 CSOUT bq24153A/8 (Top View) bq24156A/9 (Top View) Not Recommended for New Designs bq24153A, bq24156A, bq24159 5 bq24153A, bq24156A bq24158, bq24159 www.ti.com SLUSAB0D – OCTOBER 2010 – REVISED APRIL 2016 Product Folder Links: bq24153A bq24156A bq24158 bq24159 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated 7 Pin Configuration and Functions YFF Package 20-Pin Bump DSBGA Pin Functions PIN I/O DESCRIPTION NAME NO. BOOT A3 I/O Bootstrap capacitor connection for the high-side FET gate driver. Connect a 33-nF ceramic capacitor (voltage rating ≥ 10 V) from BOOT pin to SW pin. CD E2 I Charge disable control pin. CD=0, charge is enabled. CD=1, charge is disabled and VBUS pin is high impedance to GND. CSIN E1 I Charge current-sense input. Battery current is sensed across an external sense resistor. A 0.1- μF ceramic capacitor to PGND is required. CSOUT E4 I Battery voltage and current sense input. Bypass it with a ceramic capacitor (minimum 0.1 μF) to PGND if there are long inductive leads to battery. OTG (bq24153A/8 only) D4 I Boost mode enable control or input current limiting selection pin. When OTG is in active status, bq24153A/8 is forced to operate in boost mode. It has higher priority over I2C control and can be disabled using the control register. At POR while in 15-min mode, the OTG pin is default to be used as the input current limiting selection pin. The I2C register is ignored at startup. When OTG=High, IIN_LIMIT=500mA and when OTG=Low, IIN_LIMIT=100mA. PGND D1, D2, D3 Power ground PMID B1, B2, B3 I/O Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of 3.3- μF capacitor from PMID to PGND. SCL A4 I I2C interface clock. Connect a 10-k Ω pullup resistor to 1.8V rail (VAUX= VCC_HOST) SDA B4 I/O I2C interface data. Connect a 10-k Ω pullup resistor to 1.8V rail (VAUX= VCC_HOST) SLRST (bq24156A/9 only) D4 I Safety limit register reset control. When SLRST=0, bq24156A/9 resets all the safety limits (06H) to default values, regardless of the write actions to safety limits registers (06H). When SLRST=1, bq24156A/9 can program the safety limit register until any write action to other registers locks the programmed safety limits. STAT C4 O Charge status pin. Pull low when charge in progress. Open drain for other conditions. During faults, a 128- μs pulse is sent out. STAT pin can be disabled by the EN_STAT bit in control register. STAT can be used to drive a LED or communicate with a host processor. SW C1, C2, C3 O Internal switch to output inductor connection. VBUS A1, A2 I/O Charger input voltage. Bypass it with a 1- μF ceramic capacitor from VBUS to PGND. It also provides power to the load during boost mode (bq24153A/8 only) . VREF E3 O Internal bias regulator voltage. Connect a 1µF ceramic capacitor from this output to PGND. External load on VREF is not recommended. |
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