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DAC5682Z Datasheet(PDF) 3 Page - Texas Instruments |
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DAC5682Z Datasheet(HTML) 3 Page - Texas Instruments |
3 / 66 page DAC5682Z www.ti.com SLLS853F – AUGUST 2007 – REVISED JANUARY 2015 Changes from Revision B (April 2008) to Revision C Page • Changed Thermal Conductivity θJA (still air) from 22 to 20 .................................................................................................... 8 • Changed θJC from 7 to 0.2...................................................................................................................................................... 8 • Changed θJP from 0.2 to 3.5 ................................................................................................................................................... 8 • Changed DC Spec - Analog Output test condition from "without internal reference" ............................................................ 8 • Changed DC spec. REFERENCE INPUT, Small signal bandwidth conditions...................................................................... 9 • Changed Power Supply DVDD MIN from 1.71 to 1.7 and MAX from 2.15 to 1.9 .................................................................. 9 • Changed Power Supply CLKVDD MIN from 1.71 to 1.7 and MAX from 2.15 to 1.9.............................................................. 9 • Added "DC tested" to PSRR spec. ....................................................................................................................................... 10 • Added Digital latency spec. .................................................................................................................................................. 10 • Added Power-up time spec .................................................................................................................................................. 10 • Added D[15:0]P/N................................................................................................................................................................. 11 • Changed VITH+ spec .............................................................................................................................................................. 11 • Changed VITH– spec .............................................................................................................................................................. 11 • Changed IIH and IIL spec from –40 MIN and +40 MAX to ±20 TYP...................................................................................... 12 • Changed t(SCLK) term to t(SCLKL) for Low time of SCLK .......................................................................................................... 13 • Changed Clock Input Differential voltage from 0.5V to 0.4V MIN and added footnote ........................................................ 13 • Added explanatory paragraph for LVDS Inputs; prior to Figure 33 ..................................................................................... 25 • Changed Figure 34 waveform label VA,B callout .................................................................................................................. 26 • Added explanatory paragraph for Figure 35......................................................................................................................... 26 • Changed calculation for C2 Designing the PLL Loop Filter................................................................................................ 31 • Added URL link to calculator file. ......................................................................................................................................... 32 • Changed last sentence of Dual-Channel Real Upconversion paragraph............................................................................. 33 • Added modes to Dual-Channel Real Upconversion Options ............................................................................................... 33 • Added references to CDCE62005 (3 places) ...................................................................................................................... 33 • Added Multi-DAC Synchronization Procedure...................................................................................................................... 35 • Changed Recommended DAC Startup Sequence ............................................................................................................... 55 Changes from Revision A (September 2007) to Revision B Page • Changed tr(IOUT) spec. output rise time 10% to 90% typical value from 2 ns to 220 ps........................................................ 10 • Changed tf(IOUT) spec. output fall time 10% to 90% typical value from 2 ns to 220 ps ......................................................... 10 • Changed ZT spec. internal termination from 100 Ω min, 120 Ω max; to 85 Ω min, 135 Ω max........................................... 12 • Deleted temperature deratings for fDATA specifications......................................................................................................... 12 • Added DLL operating frequency range specifications.......................................................................................................... 12 • Changed In-Band SFDR vs IF, Figure 6 ............................................................................................................................. 15 • Changed CAC values from 0.1 to 0.01μF, Figure 30............................................................................................................. 23 • Changed capacitor values from 0.1 to 0.01 μF, Figure 35 ................................................................................................... 26 Changes from Original (August 2007) to Revision A Page • Changed from product preview to production data ................................................................................................................ 1 Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DAC5682Z |
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