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TMS320DM6441 Datasheet(PDF) 8 Page - Texas Instruments

Part # TMS320DM6441
Description  Digital Media System-on-Chip
Download  236 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320DM6441 Datasheet(HTML) 8 Page - Texas Instruments

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TMS320DM6441
SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010
www.ti.com
TMS320DM6441 Revision History (continued)
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 3.5.1
Table 3-12, DM6441 Default Bus Master Priorities:
Switched Central
Added, for clarity, ", DMA_PRI bit fields" to the VPSSP Default Priority Level description [Cleared
Resource (SCR) Bus
Documentation Feedback Issue]
Priorities
Added "[For more detailed information ..." statement to the VPSSP, EDMATC0P, EDMATC1P, and
C64X+_DMAP rows
Added "(MSTPRI1 Register)" to the HPIP row
Removed VICPP row with Default Priority Level of 4
Figure 3-6, MSTPRI1 Register:
Updated/changed the bit field of bits 22:20 from "RESERVED" to "HPIP"
Updated/changed the default value of bits 22:20 from "R-100" to "R/W-100"
Section 3.5.4
"The PINMUX0 pin multiplexing register controls which peripheral is given ownership ..." paragraph:
PINMUX0 Register
Updated/changed "... ownership over shared pins among EMAC, CCD, LCD, RGB888, RGB666,
Description
ATA, VLYNQ, EMIFA, and GPIO peripherals" to "... ownership over shared pins among EMAC,
CCD, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, HPI, and GPIO peripherals"
Figure 3-7, PINMUX0 Register:
Bits 4–0: Updated/changed "R/W-LLLL" to "R/W-LLLLL"
Updated/changed footnote from "For proper DM6441 device operation, always write a value of '0' to
RSV bits 30 and 29" to "For proper DM6441 device operation, always write a value of '0' to
RSV bit 30"
Table 3-14, PINMUX0 Register Field Descriptions:
Updated/changed the description of Bit 29 (HPIEN) [Cleared Documentation Feedback Issue]
Section 3.5.5
Figure 3-8, PINMUX1 Register:
PINMUX1 Register
Removed "For proper DM6441 device operation, always write a value of '0' to RSV bit 9" footnote
Description
Section 3.6
Figure 3-9, Emulation Suspend Source Register (SUSPSRC):
Emulation Control
Bits 15–13: Updated/changed "R-0000 00" to "R-000"
Section 5.3
"Measured under the following conditions:" footnote:
Electrical
Added "For more details on core and I/O activity, as well as information relevant to board power
Characteristics Over
supply design, see the TMS320DM6441 Power Consumption Summary application report
Recommended
(literature number SPRAAU3)."
Ranges of Supply
Voltage and Operating
Case Temperature
Section 6.3.1.3
Figure 6-6, PLL1 and PLL2 Clock Domain Block Diagram:
DM6441 Power and
PLL Controller 2: Updated/changed "PLLDIV1 (/1)" to "PLLDIV1 (/10)"
Clock Domains
Updated/changed "EDMA" to "EDMA3"
Section 6.3.1.4
Table 6-6, PSC Register Memory Map [Cleared Documentation Feedback Issue]:
Power and Sleep
Updated/changed address range "0x01C4 1004 through 0x01C4 1014 to "Reserved"
Controller (PSC)
Updated/changed address range "0x01C4 1100 through 0x01C4 111F to "Reserved"
Module
Updated/changed address range "0x01C4 1308 through 0x01C4 17FF to "Reserved"
Section 6.4.1
Figure 6-9, Reset Timing:
Reset Electrical
Updated/changed the pins specified in the Z Group [Cleared Documentation Feedback Issue]
Data/Timing
Section 6.6.3
Table 6-19, Switching Characteristics Over Recommended Operating Conditions for CLK_OUT1:
Clock PLL Electrical
Parameter 1 (tC): Added "ns" in UNIT column
Data/Timing (Input and
Output Clocks)
Section 6.10.1.2
Table 6-35, Switching Characteristics Over Recommended Operating Conditions for Asynchronous
EMIFA Electrical
Memory Cycles for EMIFA Module:
Data/Timing
Parameter 24 [tw(EMWEL)]: Added "ns" in UNIT column
8
Contents
Copyright © 2006–2010, Texas Instruments Incorporated
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Product Folder Link(s): TMS320DM6441


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