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TMS320DM6467 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320DM6467 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 355 page TMS320DM6467 SPRS403H – DECEMBER 2007 – REVISED JUNE 2012 www.ti.com – Absolute Time Stamp Detection • Three Configurable UART/IrDA/CIR Modules (One With Modem Control Signals) – PID Filter With 7 PID Filter Tables – Supports up to 1.8432 Mbps UART – Corresponding Clock Reference Generator (CRGEN) Modules for System Time-Clock – SIR and MIR (0.576 MBAUD) Recovery – CIR With Programmable Data Encoding • External Memory Interfaces (EMIFs) • One Serial Peripheral Interface (SPI) With Two – 297-/310.5-MHz 32-Bit DDR2 SDRAM Memory Chip-Selects Controller With 512M-Byte Address Space • Master/Slave Inter-Integrated Circuit (I2C Bus™) (1.8-V I/O) • Two Multichannel Audio Serial Ports (McASPs) – Asynchronous16-Bit-Wide EMIF (EMIFA) – One Four-Serializer Transmit/Receive Port With 128M-Byte Address Reach – One Single DIT Transmit Port for S/PDIF • Flash Memory Interfaces • 32-Bit Host Port Interface (HPI) – NOR (8-/16-Bit-Wide Data) • VLYNQ™ Interface (FPGA Interface) – NAND (8-/16-Bit-Wide Data) • Two Pulse Width Modulator (PWM) Outputs • Enhanced Direct-Memory-Access (EDMA) • ATA/ATAPI I/F (ATA/ATAPI-6 Specification) Controller (64 Independent Channels) • Up to 33 General-Purpose I/O (GPIO) Pins – Programmable Default Burst Size (Multiplexed With Other Device Functions) • 10/100/1000 Mb/s Ethernet MAC (EMAC) • On-Chip ARM ROM Bootloader (RBL) – IEEE 802.3 Compliant (3.3-V I/O Only) • Individual Power-Saving Modes for ARM/DSP – Supports MII and GMII Media Independent • Flexible PLL Clock Generators Interfaces • IEEE-1149.1 (JTAG) Boundary- – Management Data I/O (MDIO) Module Scan-Compatible • USB Port With Integrated 2.0 PHY • 529-Pin Pb-Free BGA Package – USB 2.0 High-/Full-Speed Client (CUT Suffix), 0.8-mm Ball Pitch – USB 2.0 High-/Full-/Low-Speed Host • 0.09- μm/7-Level Cu Metal Process (CMOS) (Mini-Host, Supporting One External • 3.3-V and 1.8-V I/O, 1.2-/1.05-V Internal Device) • Applications: • 32-Bit, 33-MHz, 3.3-V Peripheral Component – Video Encode/Decode/Transcode/Transrate Interconnect (PCI) Master/Slave Interface – Digital Media – Conforms to PCI Specification 2.3 – Networked Media Encode/Decode • Two 64-Bit General-Purpose Timers (Each – Video Imaging Configurable as Two 32-Bit Timers) – Video Infrastructure • One 64-Bit Watchdog Timer – Video Conferencing 2 Digital Media System-on-Chip (DMSoC) Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6467 |
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Similar Description - TMS320DM6467_17 |
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