Electronic Components Datasheet Search |
|
UPD720110AGC-8EA Datasheet(PDF) 7 Page - NEC |
|
UPD720110AGC-8EA Datasheet(HTML) 7 Page - NEC |
7 / 32 page Data Sheet S15737EJ5V0DS 7 µPD720110A (2/2) Pin Name I/O Buffer Type Active Level Function PLLLOCK O (I/O) Output Indication when PLL is locked TS(1) I Input with 12 k Ω pull-down R Test signal TS(10:2) I Input Test signal TSO I/O I/O Test signal VDD VDD AVDD VDD for analog circuit VSS VSS AVSS VSS for analog circuit N.C. Not connected Remarks 1. “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit. 2. The signal marked as “(I/O)” in the above table operates as I/O signals during testing. However, they do not need to be considered in normal use. |
Similar Part No. - UPD720110AGC-8EA |
|
Similar Description - UPD720110AGC-8EA |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |