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TPA6130A2RTJRG4 Datasheet(PDF) 7 Page - Texas Instruments |
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TPA6130A2RTJRG4 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 39 page  SCL SDA th2 t(buf) tsu2 tsu3 StartCondition StopCondition SCL SDA tw(H) tw(L) tsu1 th1 TPA6130A2 www.ti.com SLOS488F – NOVEMBER 2006 – REVISED MARCH 2015 7.7 Timing Requirements (1) (2) For I 2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCL Frequency, SCL No wait states 400 kHz tw(H) Pulse duration, SCL high 0.6 μs tw(L) Pulse duration, SCL low 1.3 μs tsu1 Setup time, SDA to SCL 300 ns th1 Hold time, SCL to SDA 10 ns t(buf) Bus free time between stop and start condition 1.3 μs tsu2 Setup time, SCL to start condition 0.6 μs th2 Hold time, start condition to SCL 0.6 μs tsu3 Setup time, SCL to stop condition 0.6 μs (1) VPull-up = VDD (2) A pull-up resistor ≤2 kΩ is required for a 5 V I2C bus voltage. Figure 1. SCL and SDA Timing Figure 2. Start and Stop Conditions Timing Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPA6130A2 |
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