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L6717ATR Datasheet(PDF) 10 Page - STMicroelectronics |
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L6717ATR Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 57 page Pins description and connection diagrams L6717A 10/57 DocID024465 Rev 1 5 FB CORE error amplifier inverting input. Connect with a resistor R FB to VSEN and with an R F - C F to COMP. Droop current for voltage positioning is sourced from this pin. 6 VSEN CORE output voltage monitor. It manages OVP and UVP protections and PWRGOOD. Connect to the positive side of the load for remote sensing. See Section 8 for details. 7FBG CORE remote ground sense. Connect to the negative side of the load for remote sensing. See Section 11 for proper layout of this connection. 8LTB LTB Technology ® input pin. Connect through an R LTB - C LTB network to the regulated voltage (CORE section) to detect load transient. See Section 12 for details. 9 NB_COMP NB error amplifier output. Connect with an R F_NB - C F_NB to NB_FB. The NB section and/or the device cannot be disabled by grounding this pin. 10 NB_FB NB error amplifier inverting input. Connect with a resistor R FB_NB to NB_VSEN and with an R F_NB - C F_NB to NB_COMP. Droop current for Voltage Positioning is sourced from this pin. 11 NB_VSEN NB output voltage monitor. It manages OVP and UVP protections and PWRGOOD. Connect to the positive side of the NB load to perform remote sensing. See Section 11 for proper layout of this connection. 12 NB_FBG NB remote ground sense. Connect to the negative side of the load to perform remote sense. See Section 11 for proper layout of this connection. 13 ILIM CORE overcurrent pin. A current I LIM =DCR/R G *I OUT proportional to the current delivered by the CORE section is sourced from this pin. The OC threshold is programmed by connecting a resistor R ILIM to SGND. When the generated voltage crosses the OC_TOT threshold (V OC_TOT = 2.5V Typ) the device latches with all MOSFETs OFF (to recover, cycle VCC or the EN pin). This pin is monitored for dynamic phase management. Filter with proper capacitor to provide OC masking time (0.5mSec typ time constant). See Section 8.4.1 for details. 14 OSC / EN / FLT OSC: It allows programming the switching frequency F SW of both Sections. Switching frequency can be increased according to the resistor R OSC connected to SGND with a gain of 10kHz/μA (see Section 9 for details). If floating, the switching frequency is 200kHz per phase. EN: Pull-low to disable the device. When set free, the device immediately checks for the VID1 status to determine the SVI / PVI protocol to be adopted and configures itself accordingly. FLT: The pin is forced high (3.3V) in case of an OV / UV fault. To recover from this condition, cycle VCC or the EN pin. Drive with open drain circuit. See Section 8 for details. Table 2. Pin description (continued) Pin# Name Function |
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