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L6759D Datasheet(PDF) 5 Page - STMicroelectronics |
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L6759D Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 51 page L6759D List of figures Doc ID 023240 Rev 1 5/51 List of figures Figure 1. Typical 3-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Typical 2-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. JMode: voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. Device initialization: default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. Device initialization: alternative sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 9. Current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 10. DVID optimization circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 11. Thermal monitor connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 12. Output current vs. switching frequency in PSK mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 13. Efficiency performances with and without enhancements (DPM, GDC) . . . . . . . . . . . . . . 36 Figure 14. ROSC vs. FSW per phase (ROSC to GND - left; ROSC to 3.3V - right) . . . . . . . . . . . . . . . . 38 Figure 15. LSLESS startup: enabled (left) and disabled (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 16. Equivalent control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 17. Control loop Bode diagram and fine tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 18. Device initialization: PMBus controlling Vout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 19. VFQFPN48 (6x6 mm) package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 |
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