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SRK2001A Datasheet(PDF) 10 Page - STMicroelectronics |
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SRK2001A Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 20 page Operation description SRK2001A 10/20 DocID029495 Rev 1 7.2 Turn-on The turn-on logic is such that each SR MOSFET is switched on when the sensed drain- source voltage goes below the VTH_ON threshold: to avoid false triggering of the gate driver, an adaptive masking delay TD_On is introduced. This delay assumes a minimum value at the high load (TD_On.min) and increases with decreasing load levels (up to TD_On.max equal to 10% of the clock cycle). Figure 5. Typical waveforms The aim of TD_On is to avoid a premature turn-on at lower load conditions, triggered by capacitive currents (due to secondary side parasitic capacitance and not really related to the current flowing through the MOSFET body diode. Figure 6 shows the effect of this parasitic: in case at the reduced load a capacitive current spike should trigger the turn-on, there would be a current inversion (flowing from the output capacitor toward the SR MOSFET). This current inversion would cause a discharge of the output capacitor and consequently an increase of the rectified current rms value, in order to balance that dis-charge; this, in turn, would affect a bit the converter efficiency. In case of SR MOSFETs with low parasitic capacitance, capacitive currents lasting less than 10% of the clock cycle are filtered: the gate drive of course will go high when the current really flows through the body diode (i.e. the comparator sensing DVS1,2 signal and referenced to the VTH_ON threshold is triggered). In case of SR MOSFETs with higher parasitic capacitance, capacitive currents lasting more than 10% of the clock cycle cannot be filtered by the turn-on delay and premature turn-on will be present. |
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