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ST10F273Z4 Datasheet(PDF) 54 Page - STMicroelectronics

Part # ST10F273Z4
Description  16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F273Z4 Datasheet(HTML) 54 Page - STMicroelectronics

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Interrupt system
ST10F273Z4
54/188
Hardware traps are exceptions or error conditions that arise during run-time. They cause
immediate non-maskable system reaction similar to a standard interrupt service (branching
to a dedicated vector table location).
The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any other program execution. Hardware trap services cannot not
be interrupted by standard interrupt or by PEC interrupts.
9.1
X-Peripheral interrupt
The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some
constraints on the implementation of the new functionality. In particular, the additional X-
Peripherals SSC1, ASC1, I2C, PWM1 and RTC need some resources to implement interrupt
and PEC transfer capabilities. For this reason, a multiplexed structure for the interrupt
management is proposed. In the next Figure 7, the principle is explained through a simple
diagram, which shows the basic structure replicated for each of the four X-interrupt available
vectors (XP0INT, XP1INT, XP2INT and XP3INT).
It is based on a set of 16-bit registers XIRxSEL (x=0,1,2,3), divided in two portions each:
Byte High
XIRxSEL[15:8]
Interrupt Enable bits
Byte Low
XIRxSEL[7:0]
Interrupt Flag bits
GPT2 timer 6
T6IR
T6IE
T6INT
00’0098h
26h
GPT2 CAPREL register
CRIR
CRIE
CRINT
00’009Ch
27h
A/D conversion complete
ADCIR
ADCIE
ADCINT
00’00A0h
28h
A/D overrun error
ADEIR
ADEIE
ADEINT
00’00A4h
29h
ASC0 transmit
S0TIR
S0TIE
S0TINT
00’00A8h
2Ah
ASC0 transmit buffer
S0TBIR
S0TBIE
S0TBINT
00’011Ch
47h
ASC0 receive
S0RIR
S0RIE
S0RINT
00’00ACh
2Bh
ASC0 error
S0EIR
S0EIE
S0EINT
00’00B0h
2Ch
SSC transmit
SCTIR
SCTIE
SCTINT
00’00B4h
2Dh
SSC receive
SCRIR
SCRIE
SCRINT
00’00B8h
2Eh
SSC error
SCEIR
SCEIE
SCEINT
00’00BCh
2Fh
PWM channel 0...3
PWMIR
PWMIE
PWMINT
00’00FCh
3Fh
See Section 9.1
XP0IR
XP0IE
XP0INT
00’0100h
40h
See Section 9.1
XP1IR
XP1IE
XP1INT
00’0104h
41h
See Section 9.1
XP2IR
XP2IE
XP2INT
00’0108h
42h
See Section 9.1
XP3IR
XP3IE
XP3INT
00’010Ch
43h
Table 30.
Interrupt sources (continued)
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number


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