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ST10F273Z4 Datasheet(PDF) 29 Page - STMicroelectronics

Part # ST10F273Z4
Description  16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F273Z4 Datasheet(HTML) 29 Page - STMicroelectronics

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ST10F273Z4
Internal Flash memory
29/188
Power supply drop
If, during a write operation, the internal low voltage supply drops below a certain internal
voltage threshold, any write operation running is suddenly interrupted and the module is
reset to Read mode. At following Power-on, the interrupted Flash write operation must be
repeated.
5.4
Register description
5.4.1
Flash control register 0 low
The Flash Control Register 0 Low (FCR0L), together with the Flash Control Register 0 High
(FCR0H), is used to enable and to monitor all the write operations on the IFlash. The user
has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by
the user in Bootstrap mode only.
FCR0L (0x0E 0000)
FCR
Reset Value: 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BSY1 BSY0 LOCK
res.
res.
res.
res.
RR
R
Table 8.
Flash control register 0 low
Bit
Function
BSY(1:0)
Bank 0:1 Busy (IFlash)
These bits indicate that a write operation is running on Bank 0 or Bank 1(IFlash). They are
automatically set when bit WMS is set. Setting Protection operation sets bits BSYx (since
protection registers are in this Block). When this bits are set, every read access to the
corresponding bank will output invalid data (software trap 009Bh), while every write access to the
bank will be ignored. At the end of the write operation or during a Program or Erase Suspend these
bits are automatically reset and the bank returns to read mode. After a Program or Erase Resume
these bits is automatically set again.
LOCK
Flash registers access locked
When this bit is set, it means that the access to the Flash Control Registers FCR0H/-FCR1H/L,
FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will
output invalid data (software trap 009Bh) and any write access will be ineffective. LOCK bit is
automatically set when the Flash bit WMS is set.
This is the only bit the user can always access to detect the status of the Flash: once it is found
low, the rest of FCR0L and all the other Flash registers are accessible by the user as well.
Note that FER content can be read when LOCK is low, but its content is updated only when also
BSYx bits are reset.


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