Copyright

© ANPEC Electronics Corp.

Rev. A.1 - Mar., 2017

www.anpec.com.tw

8

APL3227E

P IN

WLCS P1.82x 1.22

NAME

Function

A1

EN

E nabl e Pin. The d evice en te rs in shutdown mod e whe n thi s pin is tied to a high

l eve l. In th is case the o utp ut is disco nnected from the in put. To allow normal

fun ction ality, th e E N pin sha ll b e con nected to G ND to a pu ll down or to a I/O p in.

Thi s pin do es n ot ha ve an impa ct on th e fau lt detection.

B1

ACOK

O pen- Dra in Flag Ou tpu t. ACOK is driven low after in put vol tag e is stabl e

b etwee n minimum VIN an d V OVL O after de bounce . Conne ct a pullup

resistor

from A COK to the lo gic I/O voltage of th e host system. ACOK is h igh imped ance

a fter thermal shutdown.

C1

O VLO

E xtern al OVL O Ad justmen t. Co nnect O VLO to GND when u si ng th e in te rnal

thre sh old. Co nnect a re sistor-d ivid er to O VLO to se t a diffe rent O VLO thre sh old;

this exte rnal resistor-divide r is completely inde pend ent o f the internal thresh old.

A2 ,A 3,B 2

O UT

O utput Vol tag e. Ou tp ut of inte rnal swi tch. Co nnect O UT pins to gether for prope r

o peratio n.

B 3,C2 ,C3

IN

Vol tag e Inp ut. Connect IN with a 1uF ceramic cap acito r as close a s possibl e to th e

d evice . Conn ect IN pins to gether for prope r opera tio n.

A4,B4,C4

GND

G roun d. Conn ect GND pins tog ether fo r p rope r o peratio n

Pin Description

Block Diagram

IN

OUT

EN

GND

OVLO

AOCK

SEL

REFERENCE

POR

Charge

Pump

Gate Driver and

Control Logic

OTP