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TPS720 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS720 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 33 page TPS720 SBVS100E – JUNE 2008 – REVISED SEPTEMBER 2015 www.ti.com 6.2 ESD Ratings VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22- V(ESD) Electrostatic discharge ±500 V C101(2) Machine model (MM) ±100 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage (steady-state) 1.1 VBIAS or 4.5 (1) V VBIAS Bias voltage 2.5 or or VOUT + 1.4(2) 5.5 V VOUT Output voltage 0.9 3.6 V IOUT Peak output current 0 350 mA CIN Input capacitance 1 µF CBIAS Bias capacitance 0.1 µF COUT (3) Output capacitance 2.2 µF (1) Whichever is less (2) Whichever is greater (3) Maximum ESR should be less than 250 m Ω. 6.4 Thermal Information TPS720 THERMAL METRIC(1) DRV (SON) YZU (WSCP) UNIT 6 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 66.5 144.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 86.2 1.1 °C/W RθJB Junction-to-board thermal resistance 36.1 27.5 °C/W ψJT Junction-to-top characterization parameter 1.7 4.1 °C/W ψJB Junction-to-board characterization parameter 36.6 27.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.4 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 4 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: TPS720 |
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