UCC1580 datasheet(5/17 Pages) TI1

Part #	UCC1580

Description	Single Ended Active Clamp/Reset PWM

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Manufacturer	TI1 [Texas Instruments]

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UCC1580-1,-2,-3,-4

UCC2580-1,-2,-3,-4

UCC3580-1,-2,-3,-4

UVLO and Startup

For self biased off-line applications, -2 and -4 versions

(UVLO on and off thresholds of 15V and 8.5V typical)

are recommended. For all other applications, -1 and -3

versions provide the lower on threshold of 9V. The IC re-

quires a low startup current of only 160

mA when VDD is

under the UVLO threshold, enabling use of a large trickle

charge resistor (with corresponding low power dissipa-

tion) from the input voltage. VDD has an internal clamp

at 15V which can sink up to 10mA. Measures should be

taken not to exceed this current. For -2 and -4 versions,

this clamp must be activated as an indication of reaching

the UVLO on threshold. The internal reference (REF) is

brought up when the UVLO on threshold is crossed. The

startup logic ensures that LINE and REF are above and

SHTDWN is

below their respective thresholds before

outputs are asserted. LINE input is useful for monitoring

actual input voltage and shutting off the IC if it falls be-

low a programmed value. A resistive divider should be

used to connect the input voltage to the LINE input. This

feature can protect the power supply from excessive

currents at low line voltages.

Figure 1. Output time relationships.

APPLICATION INFORMATION

UDG-95070-2

Note: Waveforms are not to scale.

SS: A capacitor from SS to ground programs the soft

start time. During soft start, EAOUT follows the amplitude

of SS’s slowly increasing waveform until regulation is

achieved.

VDD: Chip power supply pin. VDD should be bypassed

to PGND. The –1 and –3 versions require VDD to ex-

ceed 9V to start and remain above 8.5V to continue run-

ning. A shunt clamp from VDD to GND limits the supply

voltage to 15V. The –2 and –4 versions do not start until

PIN DESCRIPTIONS (cont.)

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