bq26220

SLUS521B − AUGUST 2002 − REVISED FEBRUARY 2004

11

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APPLICATION INFORMATION

register interface

Information is exchanged between host system and the bq26220 through the data-register interface. See

Table 4 below. The register set consists of a 122-location address space of 8-bit bytes segmented into

Table 4. Memory Map

HDQ

ADDRESS

NAME

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

0x78−0x7F

IDROM

8 bytes of factory-programmed ROM and gain correction factor for BATH and BATL

0x73−0x77

−

Reserved

0x72

BATH

BV−SIGN

BVOS3

BVOS2

BVOS1

BVOS0

Battery voltage (bits 8 through 10)

0x71

BATL

Battery voltage (bits 0 through 7)

0x70

FPA

Flash program address byte

0x6F

FPD

Flash program data byte

0x6E

DCRH

Discharge count register-high byte

0x6D

DCRL

Discharge count register-low byte

0x6C

CCRH

Charge count register-high byte

0x6B

CCRL

Charge count register-low byte

0x6A

SCRH

Self-discharge count register-high byte

0x69

SCRL

Self−discharge count register-low byte

0x68

DTCH

Discharge timer counter register-high byte

0x67

DTCL

Discharge timer count register-low byte

0x66

CTCH

Charge timer counter register-high byte

0x65

CTCL

Charge timer counter register-low byte

0x64

MODE

GPIEN

STAT

STC

STD

WOE2

WOE1

WOE0

POR

0x63

CLR

RSVD

RSVD

RSVD

CTC

DTC

SCR

CCR

DCR

0x62

FCMD

Flash/control command register

0x61

TEMPH

Temperature-high byte (bits 0 through 2 only, other bits are reserved)

0x60

TEMPL

Temperature-low byte

0x40−0x5F

Flash

Page 2, 32 bytes of flash

0x20−0x3F

Flash

Page 1, 32 bytes of flash

0x00−0x1F

RAM/flash

Page 0, 32 bytes of flash shadowed RAM