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TPS7B6701-Q1 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS7B6701-Q1 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 26 page VIN VOUT RESET UVThres VTH(POR) VTH(RST_DLY) tRST_ DEGLITCH tRST_DELAY t <tRST_DEGLITCH tRST_ DEGLITCH VTH(RST_DLY) tRST_ DELAY Internally Set DELAY DELAY d C 1 V t 9.5 µA ´ = TPS7B6701-Q1 TPS7B6733-Q1, TPS7B6750-Q1 www.ti.com SLVSCB2C – OCTOBER 2013 – REVISED DECEMBER 2014 9.3 Feature Description 9.3.1 Enable (EN) The enable pin is a high-voltage-tolerant pin. A high input on EN actives the device and turns on the regulator. For self-bias applications, connect this input to the VIN pin. 9.3.2 Regulated Output (VOUT) The VOUT pin is the regulated output based on the required voltage. The output has current limitation. During initial power up, the regulator has a soft start incorporated to control the initial current through the pass element. In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage recovers above the minimum start-up level. 9.3.3 Power-On-Reset (RESET) The power-on-reset is an output with an external pullup resistor to the regulated supply. The reset output remains low until the regulated VO exceeds approximately 91.6% of the set value and the power-on-reset delay has expired. The regulated output falling below the 89.6% level asserts this output low after a short de-glitch time of approximately 180 µs (typical). 9.3.4 Reset Delay Timer (DELAY) An external capacitor on this pin sets the timer delay before the reset pin is asserted high. The constant output current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. If this pin is open, the default delay time is 325 µs (typical). The reset pulse delay time td, is defined with the charge time of an external capacitor DELAY (see Equation 1). (1) The power-on-reset initializes when VO exceeds 91.6% of the programmed value. The power-on-reset delay is a function of the value set by an external capacitor on the DELAY pin before the RESET pin is released high. Figure 18. Conditions to Activate RESET Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 |
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