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TPS40021-EP Datasheet(PDF) 9 Page - Texas Instruments

Part # TPS40021-EP
Description  ENHANCED, LOW-INPUT VOLTAGE-MODE SYNCHRONOUS BUCK CONTROLLER
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS40021-EP Datasheet(HTML) 9 Page - Texas Instruments

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TPS40021-EP
www.ti.com
SLUSB58 – SEPTEMBER 2012
APPLICATION INFORMATION
The TPS40021 is a low-input voltage, synchronous, voltage mode-buck controller. A typical application circuit is
shown in Figure 1. These controllers are designed to allow construction of high-performance dc-to-dc converters
with input voltages from 2.25 V to 5.5 V, and output voltages as low as 690 mV. Using a top side N-channel
MOSFET for the primary buck switch results in lower switch resistance for a given gate charge.
The device controls the delays from main switch off to rectifier turn on and from rectifier turn off to main switch
turn on in a way that minimizes diode losses (both conduction and recovery) in the synchronous rectifier. The
reduction in these losses is significant and can mean that for a given converter power level, smaller FETs can be
used, or that heat sinking can be reduced or even eliminated.
The TPS40021 is the controller of choice for most general purpose synchronous buck designs, operating in two
quadrant mode (i.e. source or sink current) full time. This device provides the best performance for output voltage
load transient response over the widest load current range.
The controller provides for a coarse short circuit current-limit function that provides pulse-by-pulse current
limiting, as well as integrates short circuit current pulses to determine the existence of a persistant fault state at
the converter output. If a fault is detected, the converter shuts down for a period of time (determined by six soft-
start cycles) and then restarts. The current-limit threshold is adjustable with a single resistor connected from VDD
to the ILIM/SYNC pin. This overcurrent function is designed to protect against catastrophic faults only, and
cannot be guaranteed to protect against all overcurrent conditions.
The controller implements a closed-loop soft start function. Startup ramp time is set by a single external capacitor
connected to the SS/SD pin. The SS/SD pin also doubles as a shutdown function.
Voltage Reference
The bandgap cell is designed with a trimmed, curvature corrected (< 1%) 0.69-V output, allowing output voltages
as low as 690 mV to be obtained.
Oscillator
The ramp waveform is a saw-tooth form at the PWM frequency with a peak voltage of 1.25 V, and a valley of
0.3 V. The PWM duty cycle is limited to a maximum of 97%, allowing the bootstrap and charge pump capacitors
to charge during every cycle.
Bootstrap/Charge Pump
The TPS40021 includes a charge pump to boost the drive voltage to the power MOSFET’s to higher levels when
the input supply is low. A capacitor connected from PVDD to PGND is the storage cap for the pump. A capacitor
connected from SW to BOOT2 gets charged every switching cycle while LDRV is high and its charge is dumped
on the PVDD capacitor when HDRV goes high. An internal switch disables the charge pump when the voltage on
PVDD reaches approximately 4.8 V and enables pumping when PVDD falls to approximately 4.6 V. The high-
side driver uses the capacitor from SW to BOOT1 as its power supply. When SW is low, this capacitor charges
from the PVDD capacitor. When the SW pin goes high, this capacitor provides above-rail drive for the high-side
N-channel FET.
PVDD, BOOT1 and BOOT2 are pre-charged to the VDD voltage during a shutdown condition. For low-input
voltage converters, utilizing higher gate threshold voltage MOSFETs, it may be necessary to add an Schottky
diode from VDD (anode) to BOOT1 to guarantee sufficient voltage for initial start up. Once switching starts the
charge pump reverses bias on the Schottky diode.
Drivers
The HDRV and LDRV MOSFET drivers are capable of driving gate-to-source voltages up to 5.0 V. Using
appropriate MOSFETs, a 25-A converter can be achieved. The LDRV driver switches between VDD and ground,
while the HDRV driver is referenced to SW and switches between BOOT1 and SW. The maximum voltage
between BOOT1 and SW is 5.0 V when PVDD is in regulation.
Copyright © 2012, Texas Instruments Incorporated
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