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TPS40192DRCTG4 Datasheet(PDF) 3 Page - Texas Instruments |
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TPS40192DRCTG4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 35 page ENABLE 1 2 3 4 5 FB COMP VDD PGD 10 9 8 7 6 HDRV SW BOOT LDRV BP5 Thermal Pad 3 TPS40192, TPS40193 www.ti.com SLUS719F – MARCH 2007 – REVISED NOVEMBER 2016 Product Folder Links: TPS40192 TPS40193 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated 5 Pin Configuration and Functions DRC Package 10-Pin VSON Top View Pin Functions PIN I/O DESCRIPTION NAME NO. BOOT 8 I Gate drive voltage for the high-side N-channel MOSFET. A capacitor 100 nF typical must be connected between this pin and SW. BP5 6 O Output bypass for the internal regulator. Connect a capacitor with a value of at least 1-μF from this pin to GND. Larger capacitors (up to 4.7-μF) can improve noise performance when using a low-side MOSFET with a gate charge of 25 nC or greater. Low power, low noise loads may be connected here if desired. The sum of the external load and the gate drive requirements must not exceed 50 mA. This regulator is turned off when ENABLE is pulled low. COMP 3 O Output of the error amplifier. ENABLE 1 I Logic level input which starts or stops the controller from an external user command. A high-level turns the controller on. A weak internal pull-up holds this pin high so that the pin may be left floating if this function is not used. FB 2 I Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference voltage (591 mV typical) HDRV 10 O Bootstrapped output for driving the gate of the high-side N-channel FET. LDRV 7 O Output to the rectifier MOSFET gate PGD 5 O Open drain power good output SW 9 I Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high- side MOSFET driver VDD 4 I Power input to the controller Thermal pad G Common reference for the device. Connect to the system GND. |
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