TPS51650RSLR datasheet(11/51 Pages) TI1

Part #	TPS51650RSLR

Description	Dual-Channel (3-Phase CPU/2-Phase GPU) SVID, D-CAP Step-Down Controller for IMVP-7 VCORE with Two Integrated Drivers

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Manufacturer	TI1 [Texas Instruments]

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11 / 51 page

TPS51650, TPS59650

www.ti.com

SLUSAV7

– JANUARY 2012

I/O

DESCRIPTION

NAME

NO.

Voltage divider to VREF. A resistor to GND sets the operating frequency of the CPU converter. The voltage level

CF-IMAX

3

I

sets the maximum operating current of the CPU converter. The IMAX value is an 8-bit A/D where VIMAX = VREF ×

IMAX / 255. Both are latched at start-up.

Voltage sense return tied for the CPU converter. Tie to GND with a 10-

Ω resistor to close feedback when the

CGFB

12

I

microprocessor is not in the socket.

Resistor to GND (RCOCP) selects 1 of 8 OCP levels (per phase, latched at start-up) of the CPU converter. Also,

COCP-R

2

I

voltage on this pin sets 1 of 8 USR/OSR levels for CPU converter.

CPGOOD

17

O

IMVP-7_PWRGD output for the CPU converter. Open-drain.

CSW1

45

I/O

Top N-channel FET gate drive return for CPU phase 1.

CSW2

40

I/O

Top N-channel FET gate drive return for CPU phase 2.

CPWM3

36

O

PWM control for the external driver, 5V logic level.

Thermal sensor connection for the CPU converter. A resistor connected to VREF forms a divider with an NTC

CTHERM

1

I/O

thermistor connected to GND.

Voltage sense line tied directly to VCORE of the CPU converter. Tie to VCORE with a 10-Ω resistor to close

CVFB

11

I

feedback when

µP is not in the socket. The soft-stop transistor is on this pin

GCOMP

27

O

Output of gM error amplifier for the GPU converter. A resistor to VREF sets the droop gain.

GCSN1

28

I

Negative current sense input for the GPU converter. Connect to the most negative node of current sense resistor

or inductor DCR sense network.

GCSN2

31

I

GCSP1

29

I

Positive current sense input for the GPU converter. Connect to the most positive node of current sense resistor

or inductor DCR sense network. Tie GCSP2 to V3R3 to disable the phase. Tie GCSP1 and GCSP2 to V3R3 to

GCSP2

30

I

disable completely the GPU converter.

Voltage sense return tied for the GPU converter. Tie to GND with a 10-

Ω resistor to close feedback when the

GGFB

25

I

microprocessor is not in the socket.

24

I

Voltage divider to VREF. R to GND sets the operating frequency of the GPU converter. The voltage level sets

GF-IMAX

the maximum operating current of the GPU converter. The IMAX value is an 8-bit A/D where VIMAX = VREF ×

IMAX / 255. Both are latched at start-up.

13

I

Resistor to GND (RGOCP) selects 1 of 8 OCP levels (per phase, latched at start-up) of the GPU converter. Also,

GOCP-R

voltage on this pin sets 1 of 8 USR/OSR levels for GPU converter.

GPGOOD

23

O

IMVP-7_PWRGD output for the GPU converter. Open-drain.

GPWM1

34

O

PWM control input for the external driver for the two phases of GPU channel (5-V logic level).

GPWM2

35

O

33

O

Skip mode control of the external driver for the GPU converter; 5-V logic level. Logic HI = FCCM; LO = SKIP. A

GSKIP

defined voltage level on this pin at start-up can turn OSR OFF or USR OFF.

32

I/O

Thermal sensor input for the GPU converter. A resistor connected to VREF forms a divider with an NTC

GTHERM

thermistor connected to GND.

26

I

Voltage sense line tied directly to VGFX of the GPU converter. Tie to VGFX with a 10-Ω resistor to close feedback

GVFB

when the microprocessor is not in the socket. The soft-stop transistor is on this pin

PGND

42

–

Synchronous N-channel FET gate drive return.

22

I

The voltage at start-up sets 1 of 7 slew rates for both converters. The SLOW rate is SLEWRATE/4. Soft-start

SLEWA

and soft-stop rates are SLEWRATE/8. This value is latched at start-up. For TPS59650, the resistor to GND sets

the base SVID address.

48

I

5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with

≥1 µF ceramic

V5

capacitor

43

I

Power input for the gate drivers; connected with an external resistor to V5F; decouple with a

≥2.2 µF ceramic

V5DRV

capacitor.

V3R3

15

I

3.3-V power input; bypass to GND with

≥1 µF ceramic cap.

37

I

Provides VBAT information to the on-time circuits for both converters. A 10-k

Ω series resistor protects the

VBAT

adjacent pins from inadvertent shorts due to solder bridges or mis-probing during test.

VCLK

18

I

SVID clock. 1-V logic level.

VDIO

20

I/O

SVID digital I/O line. 1-V logic level.

VREF

14

O

1.7-V, 500-

µA reference. Bypass to GND with a 0.22-µF ceramic capacitor.

VR_ON

16

I

IMVP-7 VR enable; 1V I/O level; 100-ns de-bounce. Regulator enters controlled soft-stop when brought low.

21

O

IMVP-7 thermal flag open drain output

– active low. Typically pulled up to 1-V logic level through 56 Ω. Fall time

VR_HOT

< 100 ns. 1-ms de-glitch using consecutive 1-ms samples.

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