TPS54521

SLVS981C – JUNE 2010 – REVISED AUGUST 2013

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PACKAGE

–40°C to 125°C

14 Pin QFN

TPS54521RHL

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

The RHL package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54521RHLR). See applications section

of data sheet for layout information.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating temperature range (unless otherwise noted)

VALUE

UNIT

VIN

–0.3 to 20

V

PVIN

–0.3 to 20

V

EN

–0.3 to 6

V

BOOT

–0.3 to 28

V

Input Voltage

VSENSE

–0.3 to 3

V

COMP

–0.3 to 3

V

PWRGD

–0.3 to 6

V

SS/TR

–0.3 to 3

V

RT/CLK

–0.3 to 6

V

BOOT-PH

0 to 8

V

Output Voltage

PH

–1 to 20

V

PH 10ns Transient

–3 to 20

V

Vdiff(GND to exposed thermal

–0.2 to 0.2

V

pad)

RT/CLK

±100

μA

Source Current

PH

Current Limit

A

PH

Current Limit

A

PVIN

Current Limit

A

Sink Current

COMP

±200

μA

PWRGD

–0.1 to 5

mA

Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A)

2

kV

Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01)

500

V

Operating Junction Temperature

–40 to 125

°C

Storage Temperature

–65 to 150

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2

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