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CD6420 Datasheet(PDF) 9 Page - Cirrus Logic |
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CD6420 Datasheet(HTML) 9 Page - Cirrus Logic |
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9 / 52 page  CS6420 DS205PP2 9 and they are post-compensated internally to pre- vent any resultant passband droop. The ADCs also expect a maximum of 1 Vrms (2.8 Vpp) at their in- puts (which are biased around 2.12 VDC). A signal of higher amplitude will clip the ADC input and may result in poor echo canceller performance. See the Design Considerations section for more details. The outputs are delta-sigma digital to analog con- verters (DACs) and have similar requirements to the ADCs. The DACs are pre-compensated to ex- pect a single-pole RC filter with a corner frequency at 4 kHz. The full scale voltage output from a DAC is 1 Vrms (2.8 Vpp) swinging around a DC bias of 2.12 V. Acoustic Interface The pins API (pin 20), APO (pin 18), MB (pin 19), and AO (pin 3) make up the Acoustic Interface. A block diagram of the Acoustic Interface is shown in Figure 4. API and APO are, respectively, the input and out- put of the built-in analog pre-amplifier. The pre- amplifier is an inverting amplifier with a fixed gain of 34 dB biased around an input offset voltage (Voff) of 2.12 V. APO is the output of the pre-am- plifier after a 1 k Ω resistor. The circuitry connected to the amplifier input must present low source im- pedance (<100 Ω) to the API pin or the gain will be reduced. When using the pre-amplifier, connecting a 0.022 µF capacitor to ground off APO will pro- vide the anti-aliasing filter required by the ADC, as shown in Figure 2. The pre-amplifier may be by- passed by clearing Mic (Register 0, bit 15) using the Microcontroller Interface (see Microcontroller In- terface section), grounding API through a capacitor, and driving APO directly. In this case, the signal into APO must be low-pass filtered by a single-pole RC filter with a corner frequency at 8 kHz (see Figure 3). Following the pre-amplifier is a programmable an- alog gain stage (PGA) which is controllable through the Microcontroller Interface. This gain 19 MB 18 APO 20 AO 0,6,9.5,12 dB ADC DAC DAC ADC D S P NI 17 NO 4 FAR-END Transmit Path Receive Path API 3.5V 2.12V 1k Ω BANDGAP 34 dB 0,6,9.5,12 dB NEAR-END 3 PGA PGA Figure 4. Analog Interface |
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