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ICS8745BI Datasheet(PDF) 1 Page - Integrated Device Technology

Part # ICS8745BI
Description  1:5 Differential-to-LVDS Zero Delay Clock Generator
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS8745BI Datasheet(HTML) 1 Page - Integrated Device Technology

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DATA SHEET
ICS8745BYI REVISION D JUNE 11, 2009
1
©2009 Integrated Device Technology, Inc.
1:5 Differential-to-LVDS Zero Delay
Clock Generator
ICS8745BI
General Description
The ICS8745BI is a highly versatile 1:5 LVDS Clock
Generator and a member of the HiPerClockS™ family
of High Performance Clock Solutions from IDT. The
ICS8745BI has a fully integrated PLL and can be
configured as zero delay buffer, multiplier or divider,
and has an output frequency range of 31.25MHz to 700MHz. The
Reference Divider, Feedback Divider and Output Divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the input
clock and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
Five differential LVDS outputs designed to meet
or exceed the requirements of ANSI TIA/EIA-644
Selectable differential clock inputs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 30ps (maximum)
Output skew: 40ps (maximum)
Static phase offset: 25ps ± 125ps
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
ICS8745BI
32-Lead LQFP 7mm x 7mm x 1.4mm
package body
Top View
Block Diagram
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
0
1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
Pullup
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pin Assignment
9
10
11 12 13
14 15 16
32
31 30
29 28
27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
Q3
nQ3
VDDO
Q2
nQ2
GND
Q1
nQ1


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