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ICS8745BI Datasheet(PDF) 12 Page - Integrated Device Technology

Part # ICS8745BI
Description  1:5 Differential-to-LVDS Zero Delay Clock Generator
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS8745BI Datasheet(HTML) 12 Page - Integrated Device Technology

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ICS8745BYI REVISION D JUNE 11, 2009
12
©2009 Integrated Device Technology, Inc.
ICS8745BI Data Sheet
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1k
Ω resistor can be used.
CLK/nCLK Input
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k
Ω resistor can be tied from CLK to ground.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100
Ω across. If they are left floating, we recommend that there
is no trace attached.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100
Ω differential
transmission line environment, LVDS drivers require a matched load
termination of 100
Ω across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
Figure 4. Typical LVDS Driver Termination
3.3V
LVDS Driver
R1
100
+
3.3V
50
50
100
Ω Differential Transmission Line


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