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ICS8745BI Datasheet(PDF) 13 Page - Integrated Device Technology

Part # ICS8745BI
Description  1:5 Differential-to-LVDS Zero Delay Clock Generator
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS8745BI Datasheet(HTML) 13 Page - Integrated Device Technology

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ICS8745BYI REVISION D JUNE 11, 2009
13
©2009 Integrated Device Technology, Inc.
ICS8745BI Data Sheet
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Schematic Example
The schematic of the ICS8745BI layout example is shown in Figure
5A. The ICS8745BI recommended PCB board layout for this example
is shown in Figure 5B. This layout example is used as a general
guideline. The layout in the actual system will depend on the selected
component types, the density of the components, the density of the
traces, and the stack up of the P.C. board.
Figure 5A. ICS8745BI LVDS Zero Delay Buffer Schematic Example
U3
8745
1
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
nQ1
Q1
GND
nQ2
Q2
VDDO
nQ3
Q3
SP = Space (i.e. not intstalled)
C16
10u
CLK_SEL
C2
0.1uF
VDDO=3.3V
C11
0.01u
RD3
SP
VDD
(U1-9)
VDD=3.3V
SEL[3:0] = 0101,
Divide by 2
RU3
1K
Zo = 50 Ohm
(77.76 MHz)
RU4
1K
RU5
SP
SEL0
RD4
SP
(155.5 MHz)
SEL2
RU6
1K
C4
0.1uF
C1
0.1uF
RU7
SP
3.3V PECL Driver
CLK_SEL
RD2
1K
RD5
1K
VDDO
SEL1
VDDO
(U1-28)
R8A
50
R7
10
R9
50
Zo = 50 Ohm
R2
100
Decoupling capacitor located near the power pins
R10
50
SEL3
RU2
SP
RD6
SP
R4
100
VDD
SEL0
(U1-32)
SEL2
C6
0.1uF
RD7
1K
Zo = 50 Ohm
SEL1
3.3V
(U1-16)
PLL_SEL
VDD
VDD
VDDA
(U1-22)
C5
0.1uF
Zo = 50 Ohm
LVDS_input
+
-


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