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ICS8745BI Datasheet(PDF) 15 Page - Integrated Device Technology

Part # ICS8745BI
Description  1:5 Differential-to-LVDS Zero Delay Clock Generator
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

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ICS8745BYI REVISION D JUNE 11, 2009
15
©2009 Integrated Device Technology, Inc.
ICS8745BI Data Sheet
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8745BI.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8745BI is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (128mA + 18mA) = 506mW
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 62mA = 215mW
Total Power_MAX = 506mW + 215mW = 721mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming a moderate air
flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.721W * 42.1°C/W = 115.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resitance θJA for 32 Lead LQFP, Forced Convection
θ
JA vs. Air Flow
Linear Feet per Minute
0200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.


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