IDT5V41315

2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER

IDT® 2 OUTPUT PCIE GEN1-2-3 SYNTHESIZER

4

IDT5V41315

MAY 8, 2017

AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1

Note 2: Measurement taken from a single-ended waveform.

Note 3: Measurement taken from a differential waveform.

Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.

Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.

Electrical Characteristics - Differential Phase Jitter Parameters

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

25

MHz

Output Frequency

HCSL termination

25

200

MHz

LVDS termination

25

100

MHz

HCSL

850

mV

HCSL

-150

mV

Absolute

250

550

mV

Variation over all edges

140

mV

80

ps

Frequency Synthesis Error

All outputs

0

ppm

±150mV

1

4

V/ns

±150mV

1

4

V/ns

125

ps

Output to Output Skew

50

ps

45

55

%

All outputs

50

100

ns

All outputs

50

100

ns

Stabilization Time

From power-up VDD=3.3 V

1.8

ms

PARAMETER

Symbol

Conditions

Min

Typ

Max

Units

Notes

PCIe Gen 1

32

86

ps (p-p) 1,2,3

PCIe Gen 2

10kHz < f < 1.5MHz

0.7

3

ps

(RMS)

1,2,3

PCIe Gen 2

1.5MHz < f < Nyquist (50MHz)

2.3

3.1

ps

(RMS)

1,2,3

PCIe Gen 3

0.6

1

ps

(RMS)

1,2,3

12kHz-20MHz

N/A

ps

(RMS)

1,2,3

Jitter, Phase