DS1670

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The Conversion Update In Progress (CU) bit in the Status Register indicates when the ADC Register can

be read. When this bit is a 1, an update to the ADC Register will occur within 488 ms maximum.

However, when this bit is 0 an update will not occur for at least 244 ms. The CU bit should be polled

before reading the ADC Register to insure that the contents are stable during a read cycle. Once a read

cycle to the ADC Register has been started, the DS1670 will not update that register until the read cycle

has been completed. It should also be mentioned that taking CS low will abort the read cycle and will

allow the ADC Register to be updated.

Figure 6 illustrates the timing of the CU bit relative to an instruction to begin conversion and the

completion of that conversion.

CU BIT TIMING Figure 6

3-WIRE SERIAL INTERFACE

Communication with the DS1670 is accomplished through a simple 3-wire interface consisting of the

Chip Select (CS), Serial Clock (SCLK) and Input/Output (I/O) pins.

All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS

turns on the control logic, which allows access to the shift register for the address/command sequence.

Second, the CS signal provides a method of terminating either single byte or multiple byte (burst) data

transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data

must be valid during the rising edge of the clock and data bits are output on the falling edge of the clock.

If the CS input goes low, all data transfer terminates and the I/O pin goes to a high impedance state.

Address and data bytes are always shifted LSB first into the I/O pin. Any transaction requires the

address/command byte to specify a read or write to a specific register followed by one or more bytes of

data. The address byte is always the first byte entered after CS is driven high. The most significant bit

cycles will occur. If this bit is 1, one or more write cycles will occur.