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ADC12DJ3200AAV Datasheet(PDF) 11 Page - Texas Instruments |
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ADC12DJ3200AAV Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 111 page  11 ADC12DJ3200 www.ti.com SLVSD97 – MAY 2017 Product Folder Links: ADC12DJ3200 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 6.5 Electrical Characteristics - DC Specifications Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC ACCURACY Resolution Resolution with no missing codes 12 bits DNL Differential nonlinearity ±0.3 LSB INL Integral nonlinearity ±2.5 LSB ANALOG INPUTS (INA+, INA–, INB+, INB–) VOFF Offset Error Default full-scale voltage, OS_CAL disabled ±0.6 mV VOFF_ADJ Input offset voltage adjustment range Available offset correction range (see OS_CAL or OADJ_x_INx) ±55 mV VOFF_DRI FT Offset Drift Foreground calibration at nominal temperature only 23 µV/°C Foreground calibration at each temperature 0 µV/°C VIN_FSR Analog differential input full scale range Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) 750 800 850 mVPP Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) 1000 1040 mVPP Minimum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0x2000) 480 500 mVPP VIN_FSR_ DRIFT Analog differential input full scale range drift Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at nominal temperature only, inputs driven by 50-Ω source, includes effect of RIN drift -0.01 %/°C Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at each temperature, inputs driven by 50-Ω source, includes effect of RIN drift 0.03 %/°C VIN_FSR_ MATCH Analog differential input full scale range matching Matching between INA+/INA– and INB+/INB–, default setting, dual channel mode 0.625 % RIN Single-ended input resistance to AGND Each input terminal is terminated to AGND 48 50 52 Ω RIN_TEMP CO Input termination linear temperature coefficient 17.6 mΩ/°C CIN Single-ended input capacitance Single channel mode at DC 0.4 pF Dual channel mode at DC 0.4 pF TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–) ΔVBE Temperature diode voltage slope Forced forward current of 100 µA. Offset voltage (approx. 0.792 V at 0°C) varies with process and must be measured for each part. Offset measurement should be done with the device unpowered or with the PD pin asserted to minimize device self-heating. PD pin should be asserted only long enough to take the offset measurement. -1.6 mV/°C BANDGAP VOLTAGE OUTPUT (BG) VBG Reference output voltage IL ≤ 100 µA 1.1 V VBG_DRIF T Reference output temperature drift IL ≤ 100 µA -64 µV/°C CLOCK INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–) ZT Internal termination Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 110 Ω Single ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 55 Ω |
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