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150060GS75000 Datasheet(PDF) 6 Page - Integrated Device Technology |
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150060GS75000 Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 35 page  P9221-R Datasheet © 2017 Integrated Device Technology, Inc. 6 April 4, 2017 Pins Name Type Function A5 RPPG I Received power packet gain (RPPG) calibration pin for foreign object detection (FOD) tuning. Connect this pin to the center tap of a resistor divider to set the gain of the FOD. The FOD is disabled by connecting the center tap of two 10kΩ resistors to VDD18 pin and GND. A6 COMM2 O Open-drain output used to communicate with the transmitter. Connect a 47nF capacitor from AC2 to COMM2. B1 RSV4 Reserved for internal use. Do not connect. B2 ALIGNY I AC input for coil alignment guide. If not used, connect to GND through a 10KΩ resistor. B3 SDA I/O I2C data pin. Open-drain output. Connect a 5.1kΩ resistor to VDD18 pin. B4 ILIM I Programmable over-current limit pin. Connect this pin to the center tap of a resistor divider to set the current limit. For more information about the current limit function, see section 8.5. B5 EN ̅̅̅̅ I Active-LOW enable pin. Pulling this pin to logic HIGH forces the device into Shut Down Mode. When connected to logic LOW, the device is enabled. Do not leave this pin floating. B6 RSV5 Reserved for internal use. Do not connect. C1, C6, J1, J2, J3,J4,J5,J6 GND GND Ground. C2 SINK O Open-drain output for controlling the rectifier clamp. Connect a 36Ω resistor from this pin to the VRECT pin. C3 INT ̅̅̅̅ O Interrupt flag pin. This is an open-drain output that signals fault interrupts. It is pulled LOW if any of these faults exists: an over-voltage is detected, an over-current condition is detected, the die temperature exceeds 140°C, or an external over-temperature condition is detected on the TS pin. It is also asserted LOW when EN is HIGH. Connect to VDD18 through a 10kΩ resistor. See section 8.6 for additional conditions affecting the interrupt flag. C4 RPPO O Received power packet offset (RPPO) calibration pin for FOD tuning. Connect to the center tap of the resistor divider to set the offset of the FOD. The FOD is disabled by connecting the center tap of two 10kΩ resistors to VDD18 pin and GND. C5 DEN I Reserved. Must connect a 10kΩ resistor to the VDD18 pin. D1, D2, D3, D4, D5, D6 OUT O Regulated output voltage pin. Connect three 10μF capacitors from this pin to GND. The default voltage is set to 12V when the VOSET pin is pulled up to VDD18 pin through a 10kΩ resister. For more information about VOSET, see section 8.2. E1, E2, E5, E6 F2, F3, F4, F5 VRECT O Output voltage of the synchronous rectifier bridge. Connect three 10μF capacitors from this pin to GND. The rectifier voltage dynamically changes as the load changes. For more information, see the typical waveforms in section 6. F1 VDD5V O Internal 5V regulator output voltage for internal use. Connect a 1μF capacitor from this pin to ground. Do not load the pin. F6 VDD18 O Internal 1.8V regulator output voltage. Connect a 1μF capacitor from this pin to ground. Do not load the pin. G1 BST1 O Boost capacitor for driving the high-side switch of the internal rectifier. Connect a 15nF capacitor from the AC1 pin to BST1. G2, H1, H2, AC1 I AC input power. Connect to the resonant capacitor (CS). G3 RSV3 I Reserved pins. Must be connected to GND. |
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