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IRM7001 Datasheet(PDF) 3 Page - Vishay Siliconix |
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IRM7001 Datasheet(HTML) 3 Page - Vishay Siliconix |
3 / 11 page Document Number: 82576 www.vishay.com Revision 17-August-01 3 Table 2. Pin Out and Signal Description Function The IRM7001 can be used in conjunction with a microcontrol- ler/microprocessor that has a serial communication interface (UART). Prior to communication the processor selects the transmission baudrate by selecting appropriate levels on the A0-A2 lines. This process sets up the communication system to operate at the prescribed data rate. After this initial step, serial data can be transmitted or received at the prescribed data rate. The IRM7001 consists of two state machines–the SIR Encode and SIR Decode blocks, and a sequential block Clock Divide, which synthesizes the required internal signal INT-CLOCK, based on the inputs A0-A2 and the CLK_ SEL line. The IRM7001 can be placed into Internal Clock Mode (CLK_SEL set to low) or External Clock Mode (CLK_ SEL set to high). The internal clock signal INT_CLOCK source is then gated appropriately through to the INT_CLOCK signal. In application where the external 16XCLK signal is provided, there is no need to provide an oscillator. The SIR Encode block is driven by TXD (negative edge trig- gered signal), which initiates the modulation state machine, resulting in the modulated IR_TXD signal (which drives the SIR compatible electronics). The SIR Decode block is driven by the IR_RCV signal (nega- tive edge triggered signal, derived from the optoelectronics). IR_RCV is demodulated by the SIR Decode block resulting in the RCV signal, which represents the stretched input pulse. In addition, there is a pin provided to the user, called the PULSEMOD. A high level input on this pin activates the 1.6us mode on the IR_TXD. In this mode, whenever there is a nega- tive edge on the TXD, the rising edge on the modulation state machine will set the IR_TXD signal high for 6 crystal clock cycles no matter what the selection on A2, A1 and A0 lines is. With a crystal frequency of 3.6864MHz, this corresponds to a high pulse of 1.63us. Signal Pin Type Description 16X CLK 1 DIGIN Positive edge triggered input clock signal that is set to 16 times the data transmission baudrate. This clock is used to drive the Encoder/Decoder state machine. Depending on the application, the 16XCLK can be provided by the application circuitry, or the internal clock divider circuitry can be used. Selection of operating mode (Internal or External clock) is selected by the CLK_SEL line. If External clock mode is selected, the application circuitry need not provide an oscillator. TXD 2 DIGIN Negative edge triggered input signal that is normally tied to the SOUT signal of a UART (serial data to be transmitted). Data is modulated and output as IR_TXD. RCV 3 DIGOUT Output signal normally tied to SIN signal of a UART (received serial data). RCV is the demodulated output of IR_RCV. A0-A2 4-6 DIGIN Clock multiplex signals. These signals are asserted to select the appropriate clock rate to support the following baudrate: 115200, 57600, 38400, 19200, 9600, 4800 and 2400 bps. CLK_SEL 7 DIGIN Active high signal, used to activate either the Internal or External clock. A high on this line activates the External clock (16XCLK), or if it is pulled low, the Internal clock is used. GND 8 Chip ground NRST 9 DIGIN Active low signal used to reset the IrDA-SIR Decode state machine. Normally this line is tied to the POR (power on reset) line of the circuit or simply to Vcc. In addition to resetting the circuitry, this signal can be asserted to disable any data reception. IR_RCV 10 DIGIN Input is from the SIR optoelectronics. Input signal is a 3/16th pulse which is demodulated (pulse stretched) to generate the RCV (3) output signal. IR_TXD 11 DIGOUT This signal is the modulated TXD signal. PULSEMOD 12 DIGIN (with pulldown) A level high on this input puts the chip into the monoshot transmit mode. In this mode, when there is a negative transition on the TXD input, a rising edge on the internal transmit modulation state ma- chine will activate a high pulse on IR_TXD for 6 crystal clock cycles. With a 3.6864MHz crystal, this corresponds to 1.63us. This mode cannot be used in conjunction with the 16XCLK clock. It is meant to be used with the external crystal clock. By default, this input pin is pulled to GND. POWER-DN 13 DIGIN (with pulldown) A high on this input puts the internal oscillator in POWERDOWN MODE. The internal oscillator nor- mally is not powered down. OSCOUT 14 ANAOUT Crystal Oscillator input OSCIN 15 ANAIN Crystal Oscillator input VCC 16 Power (see Electrical Specifications for detail) |
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