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AS4C16M16D1-5TCN Datasheet(PDF) 10 Page - Alliance Semiconductor Corporation

Part # AS4C16M16D1-5TCN
Description  Fully synchronous operation
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS4C16M16D1-5TCN Datasheet(HTML) 10 Page - Alliance Semiconductor Corporation

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AS4C16M16D1
Alliance Memory, lnc. Confidential
10
Rev. 1.1
Sep. /2011
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power
up for proper operation. The extended mode register is written by asserting low on CS , RAS , CAS , and WE .
The state of A0 ~ A12, BA0 and BA1 is written in the mode register in the same cycle as CS , RAS , CAS , and
WE going low. (the device should have all banks idle with no bursts in progress prior to writing into the mode
register, and CKE should be High). A1 is used for setting driver strength to normal, or weak. Two clock cycles
are required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for
specific codes.
Table 11. Extended Mode Register Bitmap
BA1 BA0 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0
1
RFU must be set to “0”
DS1 RFU must be set to “0” DS0 DLL Extended Mode Register
BA0
Mode
A6 A1
Drive Strength
Comment
A0
DLL
0
MRS
0
0
Full
0
Enable
1
EMRS
0
1
Weak
1
Disable
1
0
RFU
Reserved For Future
1
1 Matched impedance Output driver matches impedance


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