Electronic Components Datasheet Search |
|
AS4C256M16D3LA-12BIN Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
|
AS4C256M16D3LA-12BIN Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
2 / 83 page 256M x 16 bit DDR3L Synchronous DRAM (SDRAM) Features • JEDEC Standard Compliant • Power supplies: VDD & VDDQ = +1.35V • Backward compatible to VDD & VDDQ = 1.5V ±0.075V • Operating temperature: -40~95°C (TC) • Supports JEDEC clock jitter specification • Fully synchronous operation • Fast clock rate: 800 MHz • Differential Clock, CK & CK# • Bidirectional differential data strobe - DQS & DQS# • 8 internal banks for concurrent operation • 8n-bit prefetch architecture • Pipelined internal architecture • Precharge & active power down • Programmable Mode & Extended Mode registers • Additive Latency (AL): 0, CL-1, CL-2 • Programmable Burst lengths: 4, 8 • Burst type: Sequential / Interleave • Output Driver Impedance Control • 8192 refresh cycles / 64ms - Average refresh period 7.8μs @ -40°C ≦TC≦ +85°C 3.9μs @ +85°C <TC≦ +95°C • Write Leveling • ZQ Calibration • Dynamic ODT (Rtt_Nom & Rtt_WR) • RoHS compliant • Auto Refresh and Self Refresh • 96-ball 9 x 13 x 1.0mm FBGA package - Pb and Halogen Free Overview The 4Gb Double-Data-Rate-3 (DDR3L) DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3L DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V /+0.1V power supply and are available in BGA packages. Table 1. Ordering Information Table 2. Speed Grade Information Product part No Org Temperature Max Clock (MHz) AS4C256M16D3LA-12BIN 256M x 16 Industrial -40°C to 95°C 800 Package 96-ball FBGA Speed Grade Clock Frequency CAS Latency tRCD (ns) tRP (ns) DDR3L-1600 800 MHz 11 13.75 13.75 AS4C256M16D3LA-12BIN Confidential -2/83- Rev. 1.0 May 2016 |
Similar Part No. - AS4C256M16D3LA-12BIN |
|
Similar Description - AS4C256M16D3LA-12BIN |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |