8545-02

LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER

IDT™ / ICS™ LVDS FANOUT BUFFER

2

8545AG-02 REV. A NOVEMBER 15, 2012

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 9, 13

GND

Power

Power supply ground.

2

CLK_EN

Input

Pullup

Synchronizing clock enable. When HIGH, clock outputs follows clock input.

When LOW, Qx outputs are forced low, nQx outputs are forced high.

LVCMOS / LVTTL interface levels.

3

CLK_SEL

Input

Pulldown

Clock select input. When HIGH, selects CLK2 input.

When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels.

4

CLK1

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

5, 7

nc

Unused

No connect.

6

CLK2

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

8

OE

Input

Pullup

Output enable. Controls enabling and disabling of outputs Q0/nQ0 through

Q3/nQ3. LVCMOS/LVTTL interface levels.

10, 18

Power

Positive supply pins.

11, 12

Q3, Q3

Output

Differential output pair. LVDS interface levels.

14, 15

Q2, Q2

Output

Differential output pair. LVDS interface levels.

16, 17

Q1, Q1

Output

Differential output pair. LVDS interface levels.

19, 20

Q0, Q0

Output

Differential output pair. LVDS interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4

pF

Input Pullup Resistor

51

k



Input Pulldown Resistor

51

k

