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AS8C803600 Datasheet(PDF) 9 Page - Alliance Semiconductor Corporation |
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AS8C803600 Datasheet(HTML) 9 Page - Alliance Semiconductor Corporation |
9 / 18 page 9 AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial Temperature Range Linear Burst Sequence Table (LBO=VSS) Synchronous Write Function Truth Table(1, 2) Asynchronous Truth Table(1) Interleaved Burst SequenceTable (LBO=VDD) NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. BW3 and BW4 are not applicable other devices 3. Multiple bytes may be selected during the same cycle. NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. Synchronous function pins must be biased appropriately to satisfy operation requirements. NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. Operation GW BWE BW1 BW2 BW3 BW4 Read HHX X X X Read HL HH HH Write all Bytes L X X X X X Write all Bytes H L L L L L Write Byte 1(3) HL L H HH Write Byte 2(3) HL H L HH Write Byte 3(3) HL HHL H Write Byte 4(3) HL HH H L 5310 tbl 12 Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address (1) 11 00 0 11 0 5310 tbl 15 Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address(1) 111 0 0 1 00 5310 tbl 14 Operation(2) OE ZZ I/O Status Power Read L L Data Out Active Read H L High-Z Active Write X L High-Z – Data In Active Deselected X L High-Z Standby Sleep Mode X H High-Z Sleep 5310 tbl 13 |
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