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PC87415VCG Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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PC87415VCG Datasheet(HTML) 10 Page - National Semiconductor (TI) |
10 / 42 page 50 Configuration Registers (Continued) Reg RW Description (HEX) 1C – 1F RW BASE ADDRESS REGISTER 3 (BAR3) Used for channel 2 control block access if channel 2 is programmed to be in native mode The device decodes 4 bytes of address space for control block accesses This register is always readwrite regardless of the setting of the NativeLegacy bit in the PIF Bit 0 always 1 Bit 1 always 0 20 – 23 RW BASE ADDRESS REGISTER 4 (BAR4) Used to address the Bus Master IDE control and status registers Bit 0 always 1 Bit 1 always 0 Bit 2 always 0 Bit 3 always 0 24–3B NOT USED 3C RW INTERRUPT LINE (default is 0Eh) 3D R INTERRUPT PIN Bit 0 Always 1 Designates INTA Bit 1 – 7 0000000 3E–3F NOT USED http www nationalcom 10 |
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Similar Description - PC87415VCG |
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