Rev. PrC | Page 4 of 13

SPECIFICATIONS

AVDD1x/AVSSx = ±1.65V, 3.3V/AGND, AVDD2 - AVSSx = 2.2 V to 3.6V; IOVDD = 2.3V to 3.6V; DGND = 0V, REF = 2.5 V

internal/external, MCLK = 8192 kHz for High Resolution Mode and 4096 kHz for Low Power Mode, ODR = 128 kHz High Resolution

Table 1. Specification Table

Parameter

Test Conditions

Comment

Min

Typ

Max

Unit

ANALOG INPUTS

Differential Input Voltage Range

VREF = (REF+ − REF−)

V

Single-Ended Input Voltage

Range

0

0to VREF/

V

Common-Mode Input Range

AVSS +0.10

(AVDD1−AVSS)/2

AVDD1 – 0.10

V

Absolute AIN Voltage Limits

AVSS +0.10

AVDD1 – 0.10

DC Input Current

HR, MCLK=8192 kHz

±6

nA

LP, MCLK=4096 kHz

±2.5

nA

Differential Bias current

HR

±3

nA

LP

±1

nA

Input Current Drift

TBD

µA/°C

Input Capacitance

8pF

pF

PGA

Gain Settings

1,2,4,8

Gain drift

±3

ppm/°C

Bandwidth

Small Signal

32

kHz

Large Signal HR Mode

10

kHz

Large Signal LP Mode

3

kHz

REFERENCE

INTERNAL

Output Voltage

REF_OUT

−0.2%

2.5

+0.2%

V

Initial Accuracy

−5mV

REF_OUT

+5mV

V

Temperature Coefficient

±5

ppm/°C

Reference Load Current

−10

+10

mA

DC Power Supply Rejection

(Line Regulation)

95

dB

Load Regulation

100

µV/mA

Voltage Noise

6.8

µVrms

Voltage Noise Density

273.5

nV/√Hz

Turn-On Settling Time

100nF

1.5

ms

Long-Term Stability

1000 hours

TBD

ppm

EXTERNAL

Input Voltage

REF_IN = (REF+) – (REF−)

1

2.5V

AVDD1x

V

Buffer Headroom

AVSS + 0.1

AVDD1x−0.1

REF− Input Voltage

AVSS

AVDD1x–REFx+

V

Average REF Current

Current per channel

REF BUF DISABLED, HR

mode

18

µA/V

REF BUF PRE-Q, HR mode

200

nA/V

REF BUF DISABLED, LP

mode

4.5

µA/V

REF BUF PRE-Q, LP mode

100

nA/V

REF BUF ENABLED

120

nA/V

TEMPERATURE RANGE

Specified Performance

−40

+105

°C

AD7771

Preliminary Technical Data