TS8308500 datasheet(9/50 Pages) ATMEL

Part #	TS8308500

Description	ADC 8-bit 500 Msps

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Manufacturer	ATMEL [ATMEL Corporation]

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9

TS8308500

2193A–BDC–04/03

Timing Diagrams

Figure 2. TS8308500 Timing Diagram (500 Msps Clock Rate), Data Ready Reset, Clock Held at LOW Level

Figure 3. TS8308500 Timing Diagram (500 Msps Clock Rate), Data Ready Reset, Clock Held at HIGH Level

TC1

TC2

TA = 250 ps

X

N+1

X

N+2

X

N+3

N

DIGITAL

OUTPUTS

(VIN, VINB)

Data Ready

(DR, DRB)

(CLK, CLKB)

X

N+5

N-4

N-3

N

N-2

N-1

TC = 1000 ps

X

N+4

TOD = 1360 ps

1360 ps

DRRB

1 ns (min)

TDR = 1320 ps

TPD: 4.0 Clock periods

1000 ps

TRDR = 720 ps

N-1

TD2 = TC2+TOD-TDR

= TC2+40 ps = 540 ps

TDR = 1320 ps

DATA

N-5

N+1

TD1 = TC1+TDR-TOD

= TC1-40 ps = 460 ps

TC1

TC2

TA = 250 ps

N+1

N+2

N+3

N

DIGITAL

OUTPUTS

(VIN, VINB)

Data Ready

(DR, DRB)

(CLK, CLKB)

N+5

N-4

N-3

N

N-1

N-2

TC = 1000 ps

N+4

TOD = 1360 ps

1360 ps

DRRB

1 ns (min)

TDR = 1320 ps

TPD: 4.0 Clock periods

TRDR = 720 ps

N-1

TD2 = TC2+TOD-TD

= TC2+40 ps = 540

TDR = 1320 ps

DATA

N-5

N+1

1000 ps

X

TD1 = TC1+TDR-TOD

= TC1-40 ps = 460 ps

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