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TPS62102D Datasheet(PDF) 9 Page - Texas Instruments |
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TPS62102D Datasheet(HTML) 9 Page - Texas Instruments |
9 / 23 page TPS62100, TPS62101, TPS62102, TPS62103 MULTIMODE LOW POWER BUCK CONVERTER SLUS446B – MAY 2000 – REVISED DECEMBER 2000 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION shutdown and synchronization The TPS6210x family incorporates a dual function shutdown and synchronization pin. Pulsing the SD/SYNC pin higher than 1 V forces the internal oscillator to reset, allowing synchronization to an external signal source. It is recommended that the part not be synchronized higher than two times its nominal operating frequency. The reason for this is that synchronizing to a higher frequency causes the internal saw-tooth voltage to have less amplitude. Since this is the signal that is compared to the error-amplifier output to determine the duty cycle, the reduction in amplitude causes a corresponding increase in PWM gain as well as increased susceptibility to noise. Doubling the operating frequency through synchronization effectively cuts the saw-tooth amplitude in half, doubling the PWM gain. Bringing the SD/SYNC pin high and holding it for more than 20 µs forces the chip to enter a shutdown state. This causes almost all sections of the chip to enter a dormant state to conserve power. Bringing this pin low again allows the chip to resume operation, starting with a full soft-start cycle. This pin must not be allowed to float, since there are no internal pulldown resistors. Floating this pin could cause the device to operate erratically. error amplifier The internal error amplifier has a unity gain frequency of 3 MHz (typ). When designing a compensation network for this chip, the response of the error amplifier may be a limiting consideration. This is especially true with the 1-MHz and 2-MHz switching frequencies. The phase and gain characteristics of the error amplifier are shown in Figure 1. Due to the method of sensing voltage thresholds in the variable-frequency mode, it is recommended that the compensation loop use integral compensation (no dc path from the COMP pin to the FB pin) if the chip is allowed to automatically switch between constant- and variable-frequency modes of operation. The reason for this is to avoid dc offsets creeping into the sense point and changing the nominal output voltage in the variable-frequency mode. |
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