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X5043M8I-2.7 Datasheet(PDF) 9 Page - Xicor Inc. |
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X5043M8I-2.7 Datasheet(HTML) 9 Page - Xicor Inc. |
9 / 20 page X5043/X5045 Characteristics subject to change without notice. 9 of 20 REV 1.1.2 5/29/01 www.xicor.com Figure 9. Write Memory Sequence 24 25 26 27 28 29 30 31 SCK SI CS 012 345 67 89 10 SCK SI Instruction 8 Bit Address Data Byte 1 76 54 321 0 CS 32 33 34 35 36 37 38 39 Data Byte 2 76 543 2 10 Data Byte 3 765 4 32 10 Data Byte N 7 6 5 321 0 12 13 14 15 16 17 18 19 20 21 22 23 65 4 3 2 1 0 9th Bit of Address 8 OPERATIONAL NOTES The device powers-up in the following state: – The device is in the low power standby state. – A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. – SO pin is high impedance. – The Write Enable Latch is reset. – The Flag Bit is reset. – Reset Signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: – A WREN instruction must be issued to set the Write Enable Latch. –CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle. – Block Protect bits provide additional level of write protection for the memory array. – The WP pin LOW blocks nonvolatile write operations. |
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