FLASH MEMORY

11

Preliminary

K9G4G08U0A K9G4G08B0A

K9L8G08U1A

VALID BLOCK

NOTE :

1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is

presented wi h both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-

gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.

3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.

* : Each K9G4G08U0A chip in the K9L8G08U1A has Maximun 50 invalid blocks.

Parameter

Symbol

Min

Typ.

Max

Unit

K9G4G08X0A

1,998

-

2,048

Blocks

3,996

-

4,096

Blocks

NOTE : Capacitance is periodically sampled and not 100% tested.

Item

Symbol

Test Condition

Min

Max

Unit

Input/Output Capacitance

-

10

pF

Input Capacitance

-

10

pF

MODE SELECTION

2. WP should be biased to CMOS high or CMOS low for standby.

CLE

ALE

CE

WE

RE

WP

Mode

HL

L

H

X

Read Mode

Command Input

L

H

L

H

X

Address Input(5clock)

HL

L

H

H

Write Mode

Command Input

L

H

L

H

H

Address Input(5clock)

L

L

L

H

H

Data Input

L

L

L

H

X

Data Output

X

X

X

X

H

X

During Read(Busy)

X

XXXX

H

During Program(Busy)

X

XXXX

H

During Erase(Busy)

X

X

X

X

L

Write Protect

XX

H

X

X

Stand-by

AC TEST CONDITION

(K9XXG08XXA-XCB0 :TA=0 to 70 C, K9XXG08XXA-XIB0:TA=-40 to 85 C,

K9XXG08BXA: Vcc=2.5V~2.9V, K9XXG08UXA: Vcc=2.7V~3.6V unless otherwise)

Parameter

K9G4G08B0A

K9XXG08UXA

Input Pulse Levels

0V to Vcc

0V to Vcc

Input Rise and Fall Times

5ns

5ns

Input and Output Timing Levels

Vcc/2

Vcc/2

Output Load

1 TTL GATE and CL=30pF

1 TTL GATE and CL=50pF