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ISL6545ACRZ Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6545ACRZ Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 16 page  11 FN6305.5 April 29, 2010 The modulator transfer function is the small-signal transfer function of VOUT/VCOMP. This function is dominated by a DC gain, given by dMAXVIN/VOSC, and shaped by the output filter, with a double pole break frequency at FLC and a zero at FCE. For the purpose of this analysis, L and D represent the channel inductance and its DCR, while C and E represent the total output capacitance and its equivalent series resistance. The compensation network consists of the error amplifier (internal to the ISL6545) and the external R1-R3, C1-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase margin (better than 45°). Phase margin is the difference between the closed loop phase at F0dB and 180°. The equations that follow relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 9. Use the following guidelines for locating the poles and zeros of the compensation network: 1. Select a value for R1 (1k Ω to 5kΩ, typically). Calculate value for R2 for desired converter bandwidth (F0). If setting the output voltage via an offset resistor connected to the FB pin, Ro in Figure 9, the design procedure can be followed as presented. 2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ1 frequency (to maximize phase boost at FLC). 3. Calculate C2 such that FP1 is placed at FCE. 4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such that FP2 is placed below FSW (typically, 0.5 to 1.0 times FSW). FSW represents the switching frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter. It is recommended a mathematical model is used to plot the loop response. Check the loop gain against the error amplifier’s open-loop gain. Verify phase margin results and adjust as necessary. The equations shown in Equations 8 and 9 describe the frequency response of the modulator (GMOD), feedback compensation (GFB) and closed-loop response (GCL): COMPENSATION BREAK FREQUENCY EQUATIONS FIGURE 9. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN - + E/A VREF COMP C1 R2 R1 FB C2 R3 C3 L C VIN PWM CIRCUIT HALF-BRIDGE DRIVE OSCILLATOR E EXTERNAL CIRCUIT ISL6545 VOUT VOSC D UGATE LGATE Ro PHASE FLC 1 2 π LC ⋅ ⋅ --------------------------- = FCE 1 2 π CE ⋅⋅ ------------------------ = (EQ. 3) R2 VOSC R1 F0 ⋅⋅ dMAX VIN FLC ⋅⋅ --------------------------------------------- = (EQ. 4) C1 1 2 π R2 0.5 F LC ⋅⋅ ⋅ ----------------------------------------------- = (EQ. 5) C2 C1 2 π R2 C1 F CE 1 – ⋅⋅ ⋅ --------------------------------------------------------- = (EQ. 6) R3 R1 FSW FLC ------------ 1 – ---------------------- = C3 1 2 π R3 0.7 F SW ⋅⋅ ⋅ ------------------------------------------------- = (EQ. 7) GMOD f() dMAX VIN ⋅ VOSC ----------------------------- 1s f () EC ⋅⋅ + 1s f () ED + () C ⋅⋅ s 2 f() LC ⋅⋅ ++ ---------------------------------------------------------------------------------------- ⋅ = GFB f() 1s f () R2 C1 ⋅⋅ + sf () R1 C1 C2 + () ⋅⋅ ----------------------------------------------------- ⋅ = 1s f () R1 R3 + () C3 ⋅⋅ + 1s f () R3 C3 ⋅⋅ + () 1s f () R2 C1 C2 ⋅ C1 C2 + ---------------------- ⎝⎠ ⎛⎞ ⋅⋅ + ⎝⎠ ⎛⎞ ⋅ ---------------------------------------------------------------------------------------------------------------------------- ⋅ GCL f() GMOD f() GFB f() ⋅ = where s f () , 2 π fj ⋅⋅ = (EQ. 8) FZ1 1 2 π R2 C1 ⋅⋅ -------------------------------- = FZ2 1 2 π R1 R3 + () C3 ⋅⋅ --------------------------------------------------- = FP1 1 2 π R2 C1 C2 ⋅ C1 C2 + ---------------------- ⋅⋅ ---------------------------------------------- = FP2 1 2 π R3 C3 ⋅⋅ ------------------------------- = (EQ. 9) ISL6545, ISL6545A |
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