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CS7654 Datasheet(PDF) 16 Page - Cirrus Logic |
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CS7654 Datasheet(HTML) 16 Page - Cirrus Logic |
16 / 62 page CS7654 16 software and the device. Typically the host would write all 4 bytes to be inserted into the registers and then enable closed caption insertion and interrupts. As the closed caption interrupts occur the host soft- ware would respond by writing the next two bytes to be inserted to the correct control registers and then clear the interrupt and wait for the next field. Control Registers The control and configuration of the CS7654 is ac- complished primarily through the control register block. All of the control registers are uniquely ad- dressable via the internal address register. The con- trol register bits are initialized during device RESET. See the Programming section of this data sheet for the individual register bit allocations, bit operation- al descriptions, and initialization states. The registers of the CS7654 are located in two sep- arate Station Address ( SA ), the first one at 0x00h and the second one at 0x34h. Be careful to select the proper SA when accessing register because some registers have the same address but are locat- ed in a different Station Address. Note that both sections of this device cannot bear the same I2C ad- dress. Testability The digital circuits are completely scanned by an internal scan chain, thus providing close to 100% fault coverage. OPERATIONAL DESCRIPTION Reset Hierarchy The CS7654 is equipped with an active low asyn- chronous reset input pin, RESET. RESET is used to initialize the internal registers and the internal state machines for subsequent default operation. See the electrical and timing specification section of this data sheet for specific CS7654 device RESET and power-on signal timing requirements and restric- tions. While the RESET pin is held low, the host interface in the CS7654 is disabled and will not respond to host-initiated bus cycles. All outputs are valid after a time period following RESET pin low. A device RESET initializes the CS7654 internal registers to their default values as described by Ta- ble 13 and 14, Control Registers. In the default state, the CS7654 video DACs are disabled and the device is internally configured to provide blue field video data to the DACs (any input data present on the V [7:0] pins is ignored at this time). Otherwise, the CS7654 registers are configured for NTSC-M ITU R.BT601 output operation. At a minimum, the DAC Registers 0x04 and 0x05 at Station Address 0x00 must be written (to enable the DACs) and the IN_MODE bit of the CONTROL_0 SA 0x00, Reg- ister (0x00) must be set (to enable ITU R.BT601 data input on V [7:0]) for the CS7654 to become operational after RESET. Vertical Timing The CS7654 encoder section can be configured to operate in any of four different analog timing modes: PAL, which is 625 vertical lines, 25 frames per second interlaced; NTSC, which is 525 vertical lines, 30 frames per second interlaced; and either PAL or NTSC in Progressive Scan, in which the display is non-interlaced. These modes are selected in the CONTROL_0 Register (0x00) at SA 0x00h.Note that there are several digital mode (scaler settings ) which will not have an equivalent analog timing mode. The CS7654 conforms to standard digital decom- pression dimensions and does not process digital input data for the active analog video half lines as they are typically in the over/underscan region of televisions. 240 active lines total per field are pro- cessed for NTSC, and 288 active lines total per field are processed for PAL. Frame vertical dimen- sions are 480 lines for NTSC and 576 lines for PAL. Table 3 specifies active line numbers for both NTSC and PAL. |
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