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R-IN32M3 Datasheet(PDF) 2 Page - Renesas Technology Corp |
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R-IN32M3 Datasheet(HTML) 2 Page - Renesas Technology Corp |
2 / 116 page R-IN32M3 Series Data Sheet 1. Overview R18DS0008EJ0401 Page 2 of 110 Feb 28, 2017 1.3 Overview Table 1.2 Overview of R-IN32M3 (1/2) Product Item R-IN32M3 CPU cores ARM Cortex-M3 32-bit RISC CPU + Real-Time OS Accelerator (Hardware Real-Time OS, HW-RTOS) Operating frequency 100 MHz Instruction set Thumb Ⓡ-2 instruction ARMv7-M architecture Instruction RAM 768 Kbytes (RAM with ECC) Data RAM 512 Kbytes (RAM with ECC) Buffer RAM 64 Kbytes (RAM with ECC) Internal system bus - 32-bit system bus at 100 MHz - 128-bit communication bus at 100 MHz DMA - 4 channels + 1 channel (for real-time port) - Supports software and various interrupt-triggered DMA Boot options - Serial flash ROM boot - External memory boot - External MPU boot External memory support - 16-bit or 32-bit bus interface - Page ROM / ROM / SRAM interface - Synchronous burst memory interface - Four chip selects for external SRAM - 256-Mbyte (max) external memory space - Programmable wait function External MCU Interface - 16-bit or 32-bit bus interface - General-purpose interface for static memory - Address space:2 Mbytes (instruction RAM, data RAM, register area) Serial flash ROM memory controller - Support serial interface compatible with SPI of the companies - Support direct boot from serial memory device - Support Fast Read, Fast Read Dual Output, Fast Read Dual I/O mode - Direct layout in memory space Interrupt - 29 external interrupt pins Internal peripheral circuit I/O Ports CMOS I/O: 96 pins (max.) System timers (three systems) - Internal timer of Hardware RTOS - Internal timer of CPU - 4-channel timer array - 32-bit counter & 32-bit data register - Counter by external signal Watchdog timer - 1 channel - Software-triggered start mode - Selectable operations in response to errors: - Generation of a non-maskable interrupt (NMI) - Generation of a reset |
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