ACE24AC128

Two-wire Serial EEPROM

VER 1.1

3

Block Diagram

Pin Descriptions

(A)

Serial Clock (SCL)

The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of

this clock is to clock data out of the EEPROM device.

(B)

Device / Chip Select Addresses (A2, A1, A0)

These are the chip select input signals for the serial EEPROM devices. Typically, t hese signals are

hardwired to either V

If left unconnected, they are internally recognized as V

(C)

Serial Data Line (SDA)

SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can

be wired-OR with other open-drain output devices.

(D)

Write Protect (WP)

The ACE24AC128 devices have a WP pin to protect the whole EEPROM array from programming.

Programming operations are allowed if WP pin is left un-connected or input to V

programming functions are disabled if WP pin is connected to V

affected by the WP pin’s input level.