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BQ27750DRZT Datasheet(PDF) 10 Page - Texas Instruments |
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BQ27750DRZT Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 34 page  10 bq27750 SLUSCM7 – JUNE 2017 www.ti.com Product Folder Links: bq27750 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Current Protection Thresholds (continued) Typical values stated where TA = 25ºC, Min/Max values stated where TA = –40ºC to 85ºC (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT ΔVSCD2 SCD2 detection threshold voltage program step VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –22.2 mV VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –11.1 6.23 Current Protection Timing Typical values stated where TA = 25ºC, Min/Max values stated where TA = –40ºC to 85ºC (unless otherwise noted) PARAMETER TEST CONDITION MIN NOM MAX UNIT tOCD OCD detection delay time 1 31 ms ΔtOCD OCD detection delay time program step 2 ms tSCC SCC detection delay time 0 915 µs ΔtSCC SCC detection delay time program step 61 µs tSCD1 SCD1 detection delay time PROTECTION_CONTROL[SCDDx2] = 0 0 915 µs PROTECTION_CONTROL[SCDDx2] = 1 0 1850 ΔtSCD1 SCD1 detection delay time program step PROTECTION_CONTROL[SCDDx2] = 0 61 µs PROTECTION_CONTROL[SCDDx2] = 1 121 tSCD2 SCD2 detection delay time PROTECTION_CONTROL[SCDDx2] = 0 0 458 µs PROTECTION_CONTROL[SCDDx2] = 1 0 915 ΔtSCD2 SCD2 detection delay time program step PROTECTION_CONTROL[SCDDx2] = 0 30.5 µs PROTECTION_CONTROL[SCDDx2] = 1 61 tDETECT Current fault detect time VSRP – VSRN = VT – 3 mV for OCD, SCD1, and SC2, VSRP – VSRN = VT + 3 mV for SCC 160 µs tACC Current fault delay time accuracy Max delay setting –10% 10% 6.24 N-CH FET Drive (CHG, DSG) Typical values stated where TA = 25ºC, Min/Max values stated where TA = –40ºC to 85ºC (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT Output voltage ratio RatioDSG = (VDSG – VBAT) / VBAT, 2.2 V < VBAT < 4.07 V, 10 MΩ between PACK and DSG 2.133 2.333 2.467 — RatioCHG = (VCHG – VBAT) / VBAT, 2.2 V < VBAT < 4.07 V, 10 MΩ between BAT and CHG 2.133 2.333 2.467 V(FETON) Output voltage, CHG and DSG on VDSG(ON) = VDSG – VBAT, 4.07 V ≤ VBAT ≤ 18 V, 10 MΩ between PACK and DSG 8.75 9.5 10.25 V VCHG(ON) = VCHG – VBAT, 4.07 V ≤ VBAT ≤ 18 V, 10 MΩ between BAT and CHG 8.75 9.5 10.25 V(FETOFF) Output voltage, CHG and DSG off VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and DSG –0.4 0.4 V VCHG(OFF) = VCHG – VBAT, 10 MΩ between BAT and CHG –0.4 0.4 tR Rise time VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2 V, CL = 4.7 nF between DSG and PACK, 5.1 kΩ between DSG and CL, 10 MΩ between PACK and DSG 200 500 µs VCHG from 0% to 35% VCHG(ON)(TYP), VBAT ≥ 2.2 V, CL = 4.7 nF between CHG and BAT, 5.1 kΩ between CHG and CL, 10 MΩ between BAT and CHG 200 500 |
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