V

OUT (V)

t

DELAY

10

bq294502, bq294504, bq294512, bq294514

bq294515, bq294522, bq294524, bq294532

bq294533, bq294562, bq294572, bq294582, bq294592

SLUSAJ3F – SEPTEMBER 2011 – REVISED JUNE 2017

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Feature Description (continued)

Figure 6. Timing for Overvoltage Sensing

8.3.1 Sense Positive Input for VX

This is an input to sense each single battery cell voltage. A series resistor and a capacitor across the cell for

each input is required for noise filtering and stable voltage monitoring.

8.3.2 Output Drive, OUT

The gate of an external N-channel MOSFET is connected to this terminal. This output transitions to a high level

when an overvoltage condition is detected and after the programmed delay timer. OUT will reset to a low level if

8.3.3 Supply Input, VDD

This terminal is the unregulated input power source for the IC. A series resistor is connected to limit the current,

and a capacitor is connected to ground for noise filtering.

8.3.4 Thermal Pad, PWRPAD

8.4 Device Functional Modes

8.4.1 NORMAL Mode

When all of the cell voltages are below the overvoltage threshold, VOV, the device operates in NORMAL mode.

The device monitors the differential cell voltages connected across (V1–VSS), (V2–V1) and (V3–V2). The OUT

pin is inactive in this mode.

8.4.2 OVERVOLTAGE Mode

configured OV delay time, tDELAY. The OUT pin will pull high internally. An external FET ihen turns on, shorting

the fuse to ground, which allows the battery or charger power to blow the fuse. When all of the cell voltages fall